mips_sys

MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Tree: af62be09eb8ebe4defdd72f4595a375d6453d85c
SSH HTTPS
RSS ATOM
Download
Download .zip Download .tar Download .tar.gz
Stefan Schuermans Stefan Schuermans fix CRC generation during ethernet transmission trigger CRC generator only once per byte get CRC value _after_ last byte af62be0 @ 2012-03-07 21:15:53
..
eth.vhd implemented ethernet TX frame generation and register interface (no firmware yet, no simulation testbed support yet, not tested yet) 2012-03-05 22:01:56
rst.vhd begin of ethernet RX implementation, so far only test interface to core, does not meet timing 2012-02-20 21:16:03
rxframe.vhd implemented ethernet RX busmaster -> packet reception working 2012-03-03 23:42:55
rxif.vhd more consistent DV and CRS handling 2012-03-06 19:08:13
txframe.vhd fix CRC generation during ethernet transmission trigger CRC generator only once per byte get CRC value _after_ last byte 2012-03-07 21:15:53
txif.vhd transmit data on falling edge of ethernet TX clock 2012-03-07 21:15:19