io/eth/txif.vhd (e31652f) - mips_sys · BlinkenArea

txif.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY e_io_eth_txif IS
    PORT (
        rst:          IN  std_logic;
        clk:          IN  std_logic;
        i_data:       IN  std_logic_vector(7 DOWNTO 0);
        i_data_en:    IN  std_logic;
        o_data_ack:   OUT std_logic;
        pin_i_tx_clk: IN  std_logic;
        pin_o_txd:    OUT std_logic_vector(3 DOWNTO 0);
        pin_o_tx_en:  OUT std_logic
    );
END ENTITY e_io_eth_txif;

ARCHITECTURE a_io_eth_txif OF e_io_eth_txif IS

TYPE t_out_state IS (out_idle, out_data_l, out_data_h);

TYPE t_in_state IS (in_idle, in_wait);

SIGNAL r_out_state: t_out_state                  := out_idle;
    SIGNAL r_out_data:  std_logic_vector(7 DOWNTO 0) := X"00";

SIGNAL r_if_tx_clk_trigger: std_logic := '0';
    SIGNAL r_if_tx_clk_detect:  std_logic := '0';

SIGNAL r_if_clk_data:    std_logic_vector(7 DOWNTO 0) := X"00";
    SIGNAL r_if_clk_trigger: std_logic                    := '0';
    SIGNAL r_if_clk_detect:  std_logic                    := '0';

SIGNAL r_in_state: t_in_state := in_idle;

BEGIN

p_out: PROCESS(rst, pin_i_tx_clk)
    BEGIN
        IF rst = '1' THEN
            pin_o_txd   <= X"0";
            pin_o_tx_en <= '0';
        ELSIF falling_edge(pin_i_tx_clk) THEN
            CASE r_out_state IS
                WHEN out_idle =>
                    pin_o_txd   <= X"0";
                    pin_o_tx_en <= '0';
                WHEN out_data_l =>
                    pin_o_txd   <= r_out_data(3 DOWNTO 0);
                    pin_o_tx_en <= '1';
                WHEN out_data_h =>
                    pin_o_txd   <= r_out_data(7 DOWNTO 4);
                    pin_o_tx_en <= '1';
                WHEN OTHERS => NULL;
            END CASE;
        END IF;
    END PROCESS p_out;

p_if_tx_clk: PROCESS(rst, pin_i_tx_clk)
    BEGIN
        IF rst = '1' THEN
            r_out_state         <= out_idle;
            r_out_data          <= X"00";
            r_if_tx_clk_trigger <= '0';
            r_if_tx_clk_detect  <= '0';
        ELSIF rising_edge(pin_i_tx_clk) THEN
            CASE r_out_state IS
                WHEN out_idle =>
                    IF r_if_clk_trigger /= r_if_tx_clk_detect THEN
                        r_if_tx_clk_detect  <= NOT r_if_tx_clk_detect;
                        r_out_state         <= out_data_l;
                        r_out_data          <= r_if_clk_data;
                        r_if_tx_clk_trigger <= NOT r_if_tx_clk_trigger;
                    END IF;
                WHEN out_data_l =>
                    r_out_state <= out_data_h;
                WHEN out_data_h =>
                    IF r_if_clk_trigger /= r_if_tx_clk_detect THEN
                        r_if_tx_clk_detect  <= NOT r_if_tx_clk_detect;
                        r_out_state         <= out_data_l;
                        r_out_data          <= r_if_clk_data;
                        r_if_tx_clk_trigger <= NOT r_if_tx_clk_trigger;
                    ELSE
                        r_out_state <= out_idle;
                    END IF;
                WHEN OTHERS => NULL;
            END CASE;
        END IF;
    END PROCESS p_if_tx_clk;

p_if_clk: PROCESS(rst, clk)
    BEGIN
        IF rst = '1' THEN
            r_if_clk_data    <= X"00";
            r_if_clk_trigger <= '0';
            r_if_clk_detect  <= '0';
            r_in_state       <= in_idle;
            o_data_ack       <= '0';
        ELSIF rising_edge(clk) THEN
            o_data_ack       <= '0';
            CASE r_in_state IS
                WHEN in_idle =>
                    IF i_data_en = '1' THEN
                        r_if_clk_data    <= i_data;
                        r_if_clk_trigger <= NOT r_if_clk_trigger;
                        o_data_ack       <= '1';
                        r_in_state       <= in_wait;
                    END IF;
                WHEN in_wait =>
                    IF r_if_tx_clk_trigger /= r_if_clk_detect THEN
                        r_if_clk_detect <= NOT r_if_clk_detect;
                        IF i_data_en = '1' THEN
                            r_if_clk_data    <= i_data;
                            r_if_clk_trigger <= NOT r_if_clk_trigger;
                            o_data_ack       <= '1';
                        ELSE
                            r_in_state <= in_idle;
                        END IF;
                    END IF;
                WHEN OTHERS => NULL;
            END CASE;
        END IF;
    END PROCESS p_if_clk;

END ARCHITECTURE a_io_eth_txif;

mips_sys

transmit data on falling edge of ethernet TX clock