MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
show more eth signals
038efa2 @ 2012-03-20 22:09:21
| .. | ||
|---|---|---|
| eth.vhd | made MAC configurable in ethernet peripheral | 2012-03-11 20:48:30 |
| rst.vhd | begin of ethernet RX implementation, so far only test interface to core, does not meet timing | 2012-02-20 21:16:03 |
| rxframe.vhd | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |
| rxif.vhd | replaced ethernet RX clock domain crossing interface with dual clock FIFO | 2012-03-10 17:43:57 |
| txframe.vhd | fixed uninitialized / not resetted frame done output of ethernet TX frame processing | 2012-03-10 10:56:08 |
| txif.vhd | remove unneeded type definition | 2012-03-10 11:16:40 |