mips_sys

1) LIBRARY ieee;
2) USE ieee.std_logic_1164.all;
3) USE ieee.numeric_std.all;
4) USE std.textio.all;

5) USE work.io_lcd_pins.all;

6) USE work.io_switches_pins.all;

7) 
8) ENTITY e_testbed IS
9) END ENTITY e_testbed;
10) 
11) ARCHITECTURE a_testbed OF e_testbed IS
12) 
13)     COMPONENT e_system IS
14)         PORT (

15)             clk:              IN  std_logic;
16)             pin_o_leds:       OUT std_logic_vector(7 DOWNTO 0);
17)             pin_o_lcd:        OUT t_io_lcd_pins;
18)             pin_i_switches:   IN  t_io_switches_pins;
19)             pin_i_uart_rx:    IN  std_logic;
20)             pin_o_uart_tx:    OUT std_logic;
21)             pin_i_eth_rx_clk: IN  std_logic;
22)             pin_i_eth_rxd:    IN  std_logic_vector(4 DOWNTO 0);
23)             pin_i_eth_rx_dv:  IN  std_logic;
24)             pin_i_eth_crs:    IN  std_logic;
25)             pin_i_eth_col:    IN  std_logic;
26)             pin_i_eth_tx_clk: IN  std_logic;
27)             pin_o_eth_txd:    OUT std_logic_vector(3 DOWNTO 0);
28)             pin_o_eth_tx_en:  OUT std_logic

29)         );
30)     END COMPONENT e_system;
31) 

32)     TYPE t_eth_data IS ARRAY(0 TO 160 - 1) OF std_logic_vector(3 DOWNTO 0);
33)     CONSTANT eth_data: t_eth_data := (
34)         X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5",
35)         X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"D",
36)         X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"F",
37)         X"F", X"F", X"F", X"F", X"0", X"0", X"D", X"1",
38)         X"0", X"6", X"C", X"D", X"5", X"7", X"D", X"2",
39)         X"8", X"0", X"0", X"0", X"5", X"4", X"0", X"0",
40)         X"0", X"0", X"6", X"3", X"9", X"3", X"E", X"D",
41)         X"0", X"4", X"0", X"0", X"0", X"4", X"1", X"1",
42)         X"0", X"4", X"7", X"2", X"0", X"C", X"8", X"A",
43)         X"0", X"0", X"A", X"0", X"F", X"F", X"F", X"F",
44)         X"F", X"F", X"F", X"F", X"7", X"9", X"3", X"5",
45)         X"0", X"0", X"1", X"0", X"0", X"0", X"2", X"2",
46)         X"B", X"9", X"1", X"D", X"4", X"4", X"9", X"6",
47)         X"5", X"6", X"3", X"7", X"0", X"2", X"9", X"6",
48)         X"3", X"7", X"4", X"7", X"0", X"2", X"5", X"6",
49)         X"9", X"6", X"E", X"6", X"0", X"2", X"C", X"6",
50)         X"1", X"6", X"E", X"6", X"7", X"6", X"5", X"6",
51)         X"2", X"7", X"0", X"2", X"4", X"5", X"5", X"6",
52)         X"3", X"7", X"4", X"7", X"1", X"2", X"A", X"0",
53)         X"B", X"A", X"3", X"8", X"D", X"8", X"D", X"1"
54)         );
55) 

56)     SIGNAL s_clk:             std_logic;

57)     SIGNAL s_eth_clk:         std_logic;
58)     SIGNAL s_eth_rxd:         std_logic_vector(3 DOWNTO 0);
59)     SIGNAL s_eth_rx_dv:       std_logic;

60)     SIGNAL pin_leds:          std_logic_vector(7 DOWNTO 0);
61)     SIGNAL pin_lcd:           t_io_lcd_pins;
62)     SIGNAL pin_uart_loopback: std_logic;

63)     SIGNAL pin_eth_rxd:       std_logic_vector(4 DOWNTO 0);

64)     SIGNAL pin_eth_txd:       std_logic_vector(3 DOWNTO 0);
65)     SIGNAL pin_eth_tx_en:     std_logic;

66) 
67) BEGIN
68) 
69)     system: e_system
70)         PORT MAP (

71)             clk              => s_clk,
72)             pin_o_leds       => pin_leds,
73)             pin_o_lcd        => pin_lcd,
74)             pin_i_switches   => (sw => (OTHERS => '0'), OTHERS => '0'),
75)             pin_i_uart_rx    => pin_uart_loopback,
76)             pin_o_uart_tx    => pin_uart_loopback,

77)             pin_i_eth_rx_clk => s_eth_clk,
78)             pin_i_eth_rxd    => pin_eth_rxd,
79)             pin_i_eth_rx_dv  => s_eth_rx_dv,
80)             pin_i_eth_crs    => s_eth_rx_dv,

81)             pin_i_eth_col    => '0',

82)             pin_i_eth_tx_clk => s_eth_clk,

83)             pin_o_eth_txd    => pin_eth_txd,
84)             pin_o_eth_tx_en  => pin_eth_tx_en

85)         );
86) 

87)     pin_eth_rxd <= "0" & s_eth_rxd;
88) 
89)     p_clk: PROCESS

90)     BEGIN
91)         WHILE TRUE LOOP

92)             s_clk <= '0';

93)             WAIT FOR 10 ns;
94)             s_clk <= '1';
95)             WAIT FOR 10 ns;
96)         END LOOP;

97)     END PROCESS p_clk;
98) 
99)     p_eth_clk: PROCESS
100)     BEGIN
101)         WHILE TRUE LOOP
102)             s_eth_clk <= '0';
103)             WAIT FOR 20 ns;
104)             s_eth_clk <= '1';
105)             WAIT FOR 20 ns;
106)         END LOOP;
107)     END PROCESS p_eth_clk;
108) 
109)     p_eth_data: PROCESS
110)     BEGIN
111)         s_eth_rxd   <= "0000";
112)         s_eth_rx_dv <= '0';
113)         WAIT FOR 1 ms;
114)         WAIT UNTIL s_eth_clk = '1';
115)         WAIT UNTIL s_eth_clk = '0';
116)         FOR i IN 0 TO eth_data'length - 1 LOOP
117)             s_eth_rxd   <= eth_data(i);
118)             s_eth_rx_dv <= '1';
119)             WAIT UNTIL s_eth_clk = '1';
120)             WAIT UNTIL s_eth_clk = '0';
121)         END LOOP;
122)         s_eth_rxd   <= "0000";
123)         s_eth_rx_dv <= '0';
124)         WAIT;
125)     END PROCESS p_eth_data;

126) 
127) END ARCHITECTURE a_testbed;