test/testbed.vhd (902aa40) - mips_sys · BlinkenArea

testbed.vhd

-- MIPS I system
-- Copyright 2011-2012 Stefan Schuermans <stefan@blinkenarea.org>
-- Copyleft GNU public license V2 or later
--          http://www.gnu.org/copyleft/gpl.html

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE std.textio.all;
USE work.io_eth_pins.all;
USE work.io_lcd_pins.all;
USE work.io_switches_pins.all;

ENTITY e_testbed IS
END ENTITY e_testbed;

ARCHITECTURE a_testbed OF e_testbed IS

COMPONENT e_system IS
        PORT (
            clk:            IN  std_logic;
            pin_o_leds:     OUT std_logic_vector(7 DOWNTO 0);
            pin_o_lcd:      OUT t_io_lcd_pins;
            pin_i_switches: IN  t_io_switches_pins;
            pin_i_uart_rx:  IN  std_logic;
            pin_o_uart_tx:  OUT std_logic;
            pin_o_eth:      OUT t_io_eth_o_pins;
            pin_i_eth:      IN  t_io_eth_i_pins
        );
    END COMPONENT e_system;

-- ICMP echo request
    TYPE t_eth_data IS ARRAY(0 TO 220 - 1) OF std_logic_vector(3 DOWNTO 0);
    CONSTANT eth_data: t_eth_data := (
        X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5",
        X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"D",
        X"2", X"0", X"D", X"4", X"9", X"4", X"0", X"5",
        X"3", X"5", X"1", X"0", X"0", X"0", X"D", X"1",
        X"0", X"6", X"C", X"D", X"5", X"7", X"D", X"2",
        X"8", X"0", X"0", X"0", X"5", X"4", X"0", X"0",
        X"0", X"0", X"4", X"5", X"0", X"0", X"0", X"0",
        X"0", X"4", X"0", X"0", X"0", X"4", X"1", X"0",
        X"8", X"B", X"5", X"F", X"0", X"C", X"8", X"A",
        X"0", X"0", X"A", X"0", X"0", X"C", X"8", X"A",
        X"0", X"0", X"9", X"5", X"8", X"0", X"0", X"0",
        X"E", X"8", X"7", X"5", X"F", X"0", X"2", X"6",
        X"0", X"0", X"1", X"0", X"6", X"E", X"4", X"B",
        X"D", X"6", X"F", X"4", X"0", X"0", X"0", X"0",
        X"0", X"0", X"0", X"0", X"4", X"4", X"E", X"6",
        X"3", X"0", X"0", X"0", X"0", X"0", X"0", X"0",
        X"0", X"0", X"0", X"0", X"0", X"1", X"1", X"1",
        X"2", X"1", X"3", X"1", X"4", X"1", X"5", X"1",
        X"6", X"1", X"7", X"1", X"8", X"1", X"9", X"1",
        X"A", X"1", X"B", X"1", X"C", X"1", X"D", X"1",
        X"E", X"1", X"F", X"1", X"0", X"2", X"1", X"2",
        X"2", X"2", X"3", X"2", X"4", X"2", X"5", X"2",
        X"6", X"2", X"7", X"2", X"8", X"2", X"9", X"2",
        X"A", X"2", X"B", X"2", X"C", X"2", X"D", X"2",
        X"E", X"2", X"F", X"2", X"0", X"3", X"1", X"3",
        X"2", X"3", X"3", X"3", X"4", X"3", X"5", X"3",
        X"6", X"3", X"7", X"3", X"2", X"9", X"1", X"C",
        X"0", X"1", X"2", X"C"
        );

SIGNAL s_clk:       std_logic;
    SIGNAL s_leds:      std_logic_vector(7 DOWNTO 0);
    SIGNAL s_lcd:       t_io_lcd_pins;
    SIGNAL s_uart:      std_logic;
    SIGNAL s_o_eth:     t_io_eth_o_pins;
    SIGNAL s_i_eth:     t_io_eth_i_pins;
    SIGNAL s_eth_clk:   std_logic;
    SIGNAL s_eth_rxd_d: std_logic_vector(3 DOWNTO 0);
    SIGNAL s_eth_rx_dv: std_logic;

BEGIN

system: e_system
        PORT MAP (
            clk            => s_clk,
            pin_o_leds     => s_leds,
            pin_o_lcd      => s_lcd,
            pin_i_switches => (sw => (OTHERS => '0'), OTHERS => '0'),
            pin_i_uart_rx  => '1',
            pin_o_uart_tx  => s_uart,
            pin_i_eth      => s_i_eth,
            pin_o_eth      => s_o_eth
        );

s_i_eth.rx_clk <= s_eth_clk;
    s_i_eth.rxd    <= "0" & s_eth_rxd_d;
    s_i_eth.rx_dv  <= s_eth_rx_dv;
    s_i_eth.crs    <= s_eth_rx_dv;
    s_i_eth.col    <= '0';
    s_i_eth.tx_clk <= s_eth_clk;

p_clk: PROCESS
    BEGIN
        WHILE TRUE LOOP
            s_clk <= '0';
            WAIT FOR 10 ns;
            s_clk <= '1';
            WAIT FOR 10 ns;
        END LOOP;
    END PROCESS p_clk;

p_eth_clk: PROCESS
    BEGIN
        WHILE TRUE LOOP
            s_eth_clk <= '0';
            WAIT FOR 20 ns;
            s_eth_clk <= '1';
            WAIT FOR 20 ns;
        END LOOP;
    END PROCESS p_eth_clk;

p_eth_rx_data: PROCESS
    BEGIN
        s_eth_rxd_d <= "0000";
        s_eth_rx_dv <= '0';
        WAIT FOR 25 ms;
        WAIT UNTIL s_eth_clk = '1';
        WAIT UNTIL s_eth_clk = '0';
        FOR i IN 0 TO eth_data'length - 1 LOOP
            s_eth_rxd_d <= eth_data(i);
            s_eth_rx_dv <= '1';
            WAIT UNTIL s_eth_clk = '1';
            WAIT UNTIL s_eth_clk = '0';
        END LOOP;
        s_eth_rxd_d <= "0000";
        s_eth_rx_dv <= '0';
        WAIT;
    END PROCESS p_eth_rx_data;

p_eth_tx_data: PROCESS
        VARIABLE l: line;
    BEGIN
        FOR i IN 0 TO eth_data'length - 1 LOOP
            WAIT UNTIL s_eth_clk = '0';
            WAIT UNTIL s_eth_clk = '1';
            IF s_o_eth.tx_en = '1' THEN
                write(l, "ethernet TX: ");
                write(l, to_integer(unsigned(s_o_eth.txd)));
                writeline(output, l);
            END IF;
        END LOOP;
    END PROCESS p_eth_tx_data;

END ARCHITECTURE a_testbed;

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