MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
perl scripts to convert packet data formats, some example packets
d496995 @ 2012-03-24 13:57:41
| blocks | improve synchonous FIFO implementation (get rid of delays between reads) | 2012-03-11 18:59:11 |
|---|---|---|
| constraints | adapt ethernet TX clock timing constraint to transmission of data on falling edge | 2012-03-07 21:18:54 |
| doc | MIPS ISA spec | 2012-01-24 21:41:27 |
| fw | added padding of ethernet packets to 60 bytes data min ARP is working now | 2012-03-21 21:43:38 |
| io | made MAC configurable in ethernet peripheral | 2012-03-11 20:48:30 |
| mips | fix divider (result) | 2012-03-21 22:11:20 |
| stuff | perl scripts to convert packet data formats, some example packets | 2012-03-24 13:57:41 |
| system | implemented ethernet TX frame generation and register interface (no firmware yet, no simulation testbed support yet, not tested yet) | 2012-03-05 22:01:56 |
| test | extended testbed to log ethernet TX data | 2012-03-21 21:42:47 |
| .gitignore | impact project | 2012-02-11 00:32:06 |
| Default.wcfg | show more eth signals | 2012-03-20 22:09:21 |
| mips_sys.ipf | impact project | 2012-02-11 00:32:06 |
| mips_sys.xise | show more eth signals | 2012-03-20 22:09:21 |