MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Stefan Schuermans Stefan Schuermans implemented "register 0 is always 0" in a faster way 9a63a17 @ 2012-01-26 21:17:30
constraints start of MIPS core: begin of decoder and ALU 2012-01-23 22:06:18
doc MIPS ISA spec 2012-01-24 21:41:27
mips implemented "register 0 is always 0" in a faster way 2012-01-26 21:17:30
.gitignore start of MIPS core: begin of decoder and ALU 2012-01-23 22:06:18
mips_sys.xise compare unit, initial PC ideas 2012-01-25 18:56:29