MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
implemented "register 0 is always 0" in a faster way
9a63a17 @ 2012-01-26 21:17:30
| .. | ||
|---|---|---|
| clk.ucf | start of MIPS core: begin of decoder and ALU | 2012-01-23 22:06:18 |
| rst.ucf | start of MIPS core: begin of decoder and ALU | 2012-01-23 22:06:18 |