MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
register 0 is always 0
3b33440 @ 2012-01-26 20:42:09
| .. | ||
|---|---|---|
| alu.vhd | s operand is number of bits | 2012-01-24 21:08:12 |
| cmp.vhd | compare unit, initial PC ideas | 2012-01-25 18:56:29 |
| core.vhd | implement jump logic, implement instruction fetch | 2012-01-25 23:17:28 |
| decoder.vhd | compare unit, initial PC ideas | 2012-01-25 18:56:29 |
| regs.vhd | register 0 is always 0 | 2012-01-26 20:42:09 |
| shifter.vhd | separated shifter from ALU | 2012-01-24 20:43:21 |
| types.vhd | compare unit, initial PC ideas | 2012-01-25 18:56:29 |