implement jump logic, implement instruction fetch (598eb97) - mips_sys · BlinkenArea

mips/core.vhd

@@ -7,7 +7,8 @@ ENTITY e_mips_core IS
     PORT (
         rst:          IN  std_logic;
         clk:          IN  std_logic;
-        o_res: OUT std_logic_vector(31 DOWNTO 0)
+        o_instr_addr: OUT std_logic_vector(31 DOWNTO 0);
+        i_instr_data: IN  std_logic_vector(31 DOWNTO 0)
     );
 END ENTITY e_mips_core;
 
@@ -16,19 +17,31 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
     SIGNAL r_pc: std_logic_vector(31 DOWNTO 0);
     SIGNAL n_pc: std_logic_vector(31 DOWNTO 0);
 
-    SIGNAL r_instr: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_instr: std_logic_vector(31 DOWNTO 0);
+
+    SIGNAL n_reg_s:  std_logic_vector( 4 DOWNTO 0);
+    SIGNAL n_reg_t:  std_logic_vector( 4 DOWNTO 0);
+    SIGNAL n_reg_d:  std_logic_vector( 4 DOWNTO 0);
+    SIGNAL n_imm_a:  std_logic_vector( 4 DOWNTO 0);
+    SIGNAL n_imm_16: std_logic_vector(15 DOWNTO 0);
+    SIGNAL n_imm_26: std_logic_vector(25 DOWNTO 0);
+    SIGNAL n_op:     t_op;
+    SIGNAL n_link:   t_link;
+    SIGNAL n_cmp:    t_cmp;
+    SIGNAL n_alu:    t_alu;
+    SIGNAL n_imm:    t_imm;
 
-    SIGNAL s_reg_s:  std_logic_vector( 4 DOWNTO 0);
-    SIGNAL s_reg_t:  std_logic_vector( 4 DOWNTO 0);
-    SIGNAL s_reg_d:  std_logic_vector( 4 DOWNTO 0);
-    SIGNAL s_imm_a:  std_logic_vector( 4 DOWNTO 0);
-    SIGNAL s_imm_16: std_logic_vector(15 DOWNTO 0);
-    SIGNAL s_imm_26: std_logic_vector(25 DOWNTO 0);
-    SIGNAL s_op:     t_op;
-    SIGNAL s_link:   t_link;
-    SIGNAL s_cmp:    t_cmp;
-    SIGNAL s_alu:    t_alu;
-    SIGNAL s_imm:    t_imm;
+    SIGNAL r_reg_s:  std_logic_vector( 4 DOWNTO 0);
+    SIGNAL r_reg_t:  std_logic_vector( 4 DOWNTO 0);
+    SIGNAL r_reg_d:  std_logic_vector( 4 DOWNTO 0);
+    SIGNAL r_imm_a:  std_logic_vector( 4 DOWNTO 0);
+    SIGNAL r_imm_16: std_logic_vector(15 DOWNTO 0);
+    SIGNAL r_imm_26: std_logic_vector(25 DOWNTO 0);
+    SIGNAL r_op:     t_op;
+    SIGNAL r_link:   t_link;
+    SIGNAL r_cmp:    t_cmp;
+    SIGNAL r_alu:    t_alu;
+    SIGNAL r_imm:    t_imm;
 
     SIGNAL s_val_s: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_val_t: std_logic_vector(31 DOWNTO 0);
@@ -98,27 +111,27 @@ BEGIN
 
     decoder: e_mips_decoder
         PORT MAP (
-            i_instr  => r_instr,
-            o_reg_s  => s_reg_s,
-            o_reg_t  => s_reg_t,
-            o_reg_d  => s_reg_d,
-            o_imm_a  => s_imm_a,
-            o_imm_16 => s_imm_16,
-            o_imm_26 => s_imm_26,
-            o_op     => s_op,
-            o_link   => s_link,
-            o_cmp    => s_cmp,
-            o_alu    => s_alu,
-            o_imm    => s_imm
+            i_instr  => s_instr,
+            o_reg_s  => n_reg_s,
+            o_reg_t  => n_reg_t,
+            o_reg_d  => n_reg_d,
+            o_imm_a  => n_imm_a,
+            o_imm_16 => n_imm_16,
+            o_imm_26 => n_imm_26,
+            o_op     => n_op,
+            o_link   => n_link,
+            o_cmp    => n_cmp,
+            o_alu    => n_alu,
+            o_imm    => n_imm
         );
 
     regs: e_mips_regs
         PORT MAP (
             rst         => rst,
             clk         => clk,
-            i_rd_a_no   => s_reg_s,
+            i_rd_a_no   => r_reg_s,
             o_rd_a_data => s_val_s,
-            i_rd_b_no   => s_reg_t,
+            i_rd_b_no   => r_reg_t,
             o_rd_b_data => s_val_t,
             i_wr_no     => s_reg_wr_no,
             i_wr_data   => s_reg_wr_data,
@@ -127,7 +140,7 @@ BEGIN
 
     alu: e_mips_alu
         PORT MAP (
-            i_alu => s_alu,
+            i_alu => r_alu,
             i_op1 => s_alu_op1,
             i_op2 => s_alu_op2,
             o_res => s_alu_res
@@ -135,71 +148,105 @@ BEGIN
 
     cmp: e_mips_cmp
         PORT MAP (
-            i_cmp => s_cmp,
+            i_cmp => r_cmp,
             i_op1 => s_cmp_op1,
             i_op2 => s_cmp_op2,
             o_res => s_cmp_res
         );
 
-    p_dummy_fetch: PROCESS(rst, clk)
+    p_sync_pc: PROCESS(rst, clk)
+    BEGIN
+        IF rst = '1' THEN
+            r_pc <= (OTHERS => '0');
+        ELSIF rising_edge(clk) THEN
+            r_pc <= n_pc;
+        END IF;
+    END PROCESS p_sync_pc;
+
+    p_fetch: PROCESS(n_pc, i_instr_data)
+    BEGIN
+        o_instr_addr <= n_pc;
+        s_instr      <= i_instr_data;
+    END PROCESS p_fetch;
+
+    p_dec2ex: PROCESS(rst, clk)
     BEGIN
         IF rst = '1' THEN
-            r_instr <= (OTHERS => '0');
+            r_reg_s  <= (OTHERS => '0');
+            r_reg_t  <= (OTHERS => '0');
+            r_reg_d  <= (OTHERS => '0');
+            r_imm_a  <= (OTHERS => '0');
+            r_imm_16 <= (OTHERS => '0');
+            r_imm_26 <= (OTHERS => '0');
+            r_op     <= op_none;
+            r_link   <= link_none;
+            r_cmp    <= cmp_none;
+            r_alu    <= alu_none;
+            r_imm    <= imm_none;
         ELSIF rising_edge(clk) THEN
-            r_instr <= std_logic_vector(unsigned(r_instr) +
-                                        to_unsigned(1, 32));
+            r_reg_s  <= n_reg_s;
+            r_reg_t  <= n_reg_t;
+            r_reg_d  <= n_reg_d;
+            r_imm_a  <= n_imm_a;
+            r_imm_16 <= n_imm_16;
+            r_imm_26 <= n_imm_26;
+            r_op     <= n_op;
+            r_link   <= n_link;
+            r_cmp    <= n_cmp;
+            r_alu    <= n_alu;
+            r_imm    <= n_imm;
         END IF;
-    END PROCESS p_dummy_fetch;
+    END PROCESS p_dec2ex;
 
-    p_alu_in: PROCESS(s_op, s_imm, s_val_s, s_val_t, s_imm_a, s_imm_16)
+    p_alu_in: PROCESS(r_op, r_imm, s_val_s, s_val_t, r_imm_a, r_imm_16)
     BEGIN
         s_alu_op1 <= (OTHERS => '0');
         s_alu_op2 <= (OTHERS => '0');
-        IF s_op = op_alu THEN
-            CASE s_imm IS
+        IF r_op = op_alu THEN
+            CASE r_imm IS
                 WHEN imm_none =>
                     s_alu_op1 <= s_val_s;
                     s_alu_op2 <= s_val_t;
                 WHEN imm_a =>
-                    s_alu_op1(4 DOWNTO 0) <= s_imm_a;
+                    s_alu_op1(4 DOWNTO 0) <= r_imm_a;
                     s_alu_op2 <= s_val_t;
                 WHEN imm_16se =>
                     s_alu_op1 <= s_val_s;
-                    s_alu_op2(15 DOWNTO 0) <= s_imm_16;
-                    IF (s_imm_16(15) = '1') THEN
+                    s_alu_op2(15 DOWNTO 0) <= r_imm_16;
+                    IF (r_imm_16(15) = '1') THEN
                         s_alu_op2(31 DOWNTO 16) <= (OTHERS => '1');
                     END IF;
                 WHEN imm_16ze =>
                     s_alu_op1 <= s_val_s;
-                    s_alu_op2(15 DOWNTO 0) <= s_imm_16;
+                    s_alu_op2(15 DOWNTO 0) <= r_imm_16;
                 WHEN OTHERS => NULL;
             END CASE;
         END IF;
     END PROCESS p_alu_in;
 
-    p_cmp_in: PROCESS(s_op, s_val_s, s_val_t)
+    p_cmp_in: PROCESS(r_op, s_val_s, s_val_t)
     BEGIN
         s_cmp_op1 <= (OTHERS => '0');
         s_cmp_op2 <= (OTHERS => '0');
-        IF s_op = op_j THEN
+        IF r_op = op_j THEN
             s_cmp_op1 <= s_val_s;
             s_cmp_op2 <= s_val_t;
         END IF;
     END PROCESS p_cmp_in;
 
-    p_reg_wr: PROCESS(s_op, s_imm, s_reg_t, s_reg_d)
+    p_reg_wr: PROCESS(r_op, r_imm, r_reg_t, r_reg_d)
     BEGIN
         s_reg_wr_no   <= (OTHERS => '0');
         s_reg_wr_data <= (OTHERS => '0');
         s_reg_wr_en   <= '0';
-        IF s_op = op_alu THEN
-            CASE s_imm IS
+        IF r_op = op_alu THEN
+            CASE r_imm IS
                 WHEN imm_none | imm_a =>
-                    s_reg_wr_no   <= s_reg_d;
+                    s_reg_wr_no   <= r_reg_d;
                     s_reg_wr_data <= s_alu_res;
                     s_reg_wr_en   <= '1';
                 WHEN imm_16se | imm_16ze =>
-                    s_reg_wr_no   <= s_reg_t;
+                    s_reg_wr_no   <= r_reg_t;
                     s_reg_wr_data <= s_alu_res;
                     s_reg_wr_en   <= '1';
                 WHEN OTHERS => NULL;
@@ -207,34 +254,21 @@ BEGIN
         END IF;
     END PROCESS p_reg_wr;
 
-    p_next_pc: PROCESS(s_op, s_imm, s_cmp_res, s_imm_16, s_imm_26)
+    p_next_pc: PROCESS(r_pc, r_op, r_imm, s_cmp_res, r_imm_16, r_imm_26)
         VARIABLE v_pc:  signed(31 DOWNTO 0);
         VARIABLE v_rel: signed(17 DOWNTO 0);
     BEGIN
-        -- FIXME
-        IF s_cmp_res = '1' AND s_imm = imm_26 THEN
-            n_pc <= r_pc(31 DOWNTO 28) & s_imm_26 & "00";
+        IF r_op = op_j AND s_cmp_res = '1' THEN
+            IF r_imm = imm_26 THEN
+                n_pc <= r_pc(31 DOWNTO 28) & r_imm_26 & "00";
             ELSE
-            v_pc := signed(r_pc);
-            v_rel := to_signed(4, 18);
-            IF s_cmp_res = '1' THEN
-                v_rel := signed(s_imm_16 & "00");
+                n_pc <= std_logic_vector(signed(r_pc) +
+                                         signed(r_imm_16 & "00"));
             END IF;
-            v_pc := v_pc + v_rel;
-            n_pc <= std_logic_vector(v_pc);
+        ELSE
+            n_pc <= std_logic_vector(signed(r_pc) + to_signed(4, 32));
         END IF;
     END PROCESS p_next_pc;
 
-    p_sync: PROCESS(rst, clk)
-    BEGIN
-        IF rst = '1' THEN
-            r_pc <= (OTHERS => '0');
-        ELSIF rising_edge(clk) THEN
-            r_pc <= n_pc;
-        END IF;
-    END PROCESS p_sync;
-
-    o_res <= s_alu_res;
-
 END ARCHITECTURE a_mips_core;
 


...	...	@@ -7,7 +7,8 @@ ENTITY e_mips_core IS
7	7	PORT (
8	8	rst: IN std_logic;
9	9	clk: IN std_logic;
10		- o_res: OUT std_logic_vector(31 DOWNTO 0)
	10	+ o_instr_addr: OUT std_logic_vector(31 DOWNTO 0);
	11	+ i_instr_data: IN std_logic_vector(31 DOWNTO 0)
11	12	);
12	13	END ENTITY e_mips_core;
13	14
...	...	@@ -16,19 +17,31 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
16	17	SIGNAL r_pc: std_logic_vector(31 DOWNTO 0);
17	18	SIGNAL n_pc: std_logic_vector(31 DOWNTO 0);
18	19
19		- SIGNAL r_instr: std_logic_vector(31 DOWNTO 0);
	20	+ SIGNAL s_instr: std_logic_vector(31 DOWNTO 0);
	21	+
	22	+ SIGNAL n_reg_s: std_logic_vector( 4 DOWNTO 0);
	23	+ SIGNAL n_reg_t: std_logic_vector( 4 DOWNTO 0);
	24	+ SIGNAL n_reg_d: std_logic_vector( 4 DOWNTO 0);
	25	+ SIGNAL n_imm_a: std_logic_vector( 4 DOWNTO 0);
	26	+ SIGNAL n_imm_16: std_logic_vector(15 DOWNTO 0);
	27	+ SIGNAL n_imm_26: std_logic_vector(25 DOWNTO 0);
	28	+ SIGNAL n_op: t_op;
	29	+ SIGNAL n_link: t_link;
	30	+ SIGNAL n_cmp: t_cmp;
	31	+ SIGNAL n_alu: t_alu;
	32	+ SIGNAL n_imm: t_imm;
20	33
21		- SIGNAL s_reg_s: std_logic_vector( 4 DOWNTO 0);
22		- SIGNAL s_reg_t: std_logic_vector( 4 DOWNTO 0);
23		- SIGNAL s_reg_d: std_logic_vector( 4 DOWNTO 0);
24		- SIGNAL s_imm_a: std_logic_vector( 4 DOWNTO 0);
25		- SIGNAL s_imm_16: std_logic_vector(15 DOWNTO 0);
26		- SIGNAL s_imm_26: std_logic_vector(25 DOWNTO 0);
27		- SIGNAL s_op: t_op;
28		- SIGNAL s_link: t_link;
29		- SIGNAL s_cmp: t_cmp;
30		- SIGNAL s_alu: t_alu;
31		- SIGNAL s_imm: t_imm;
	34	+ SIGNAL r_reg_s: std_logic_vector( 4 DOWNTO 0);
	35	+ SIGNAL r_reg_t: std_logic_vector( 4 DOWNTO 0);
	36	+ SIGNAL r_reg_d: std_logic_vector( 4 DOWNTO 0);
	37	+ SIGNAL r_imm_a: std_logic_vector( 4 DOWNTO 0);
	38	+ SIGNAL r_imm_16: std_logic_vector(15 DOWNTO 0);
	39	+ SIGNAL r_imm_26: std_logic_vector(25 DOWNTO 0);
	40	+ SIGNAL r_op: t_op;
	41	+ SIGNAL r_link: t_link;
	42	+ SIGNAL r_cmp: t_cmp;
	43	+ SIGNAL r_alu: t_alu;
	44	+ SIGNAL r_imm: t_imm;
32	45
33	46	SIGNAL s_val_s: std_logic_vector(31 DOWNTO 0);
34	47	SIGNAL s_val_t: std_logic_vector(31 DOWNTO 0);
...	...	@@ -98,27 +111,27 @@ BEGIN
98	111
99	112	decoder: e_mips_decoder
100	113	PORT MAP (
101		- i_instr => r_instr,
102		- o_reg_s => s_reg_s,
103		- o_reg_t => s_reg_t,
104		- o_reg_d => s_reg_d,
105		- o_imm_a => s_imm_a,
106		- o_imm_16 => s_imm_16,
107		- o_imm_26 => s_imm_26,
108		- o_op => s_op,
109		- o_link => s_link,
110		- o_cmp => s_cmp,
111		- o_alu => s_alu,
112		- o_imm => s_imm
	114	+ i_instr => s_instr,
	115	+ o_reg_s => n_reg_s,
	116	+ o_reg_t => n_reg_t,
	117	+ o_reg_d => n_reg_d,
	118	+ o_imm_a => n_imm_a,
	119	+ o_imm_16 => n_imm_16,
	120	+ o_imm_26 => n_imm_26,
	121	+ o_op => n_op,
	122	+ o_link => n_link,
	123	+ o_cmp => n_cmp,
	124	+ o_alu => n_alu,
	125	+ o_imm => n_imm
113	126	);
114	127
115	128	regs: e_mips_regs
116	129	PORT MAP (
117	130	rst => rst,
118	131	clk => clk,
119		- i_rd_a_no => s_reg_s,
	132	+ i_rd_a_no => r_reg_s,
120	133	o_rd_a_data => s_val_s,
121		- i_rd_b_no => s_reg_t,
	134	+ i_rd_b_no => r_reg_t,
122	135	o_rd_b_data => s_val_t,
123	136	i_wr_no => s_reg_wr_no,
124	137	i_wr_data => s_reg_wr_data,
...	...	@@ -127,7 +140,7 @@ BEGIN
127	140
128	141	alu: e_mips_alu
129	142	PORT MAP (
130		- i_alu => s_alu,
	143	+ i_alu => r_alu,
131	144	i_op1 => s_alu_op1,
132	145	i_op2 => s_alu_op2,
133	146	o_res => s_alu_res
...	...	@@ -135,71 +148,105 @@ BEGIN
135	148
136	149	cmp: e_mips_cmp
137	150	PORT MAP (
138		- i_cmp => s_cmp,
	151	+ i_cmp => r_cmp,
139	152	i_op1 => s_cmp_op1,
140	153	i_op2 => s_cmp_op2,
141	154	o_res => s_cmp_res
142	155	);
143	156
144		- p_dummy_fetch: PROCESS(rst, clk)
	157	+ p_sync_pc: PROCESS(rst, clk)
	158	+ BEGIN
	159	+ IF rst = '1' THEN
	160	+ r_pc <= (OTHERS => '0');
	161	+ ELSIF rising_edge(clk) THEN
	162	+ r_pc <= n_pc;
	163	+ END IF;
	164	+ END PROCESS p_sync_pc;
	165	+
	166	+ p_fetch: PROCESS(n_pc, i_instr_data)
	167	+ BEGIN
	168	+ o_instr_addr <= n_pc;
	169	+ s_instr <= i_instr_data;
	170	+ END PROCESS p_fetch;
	171	+
	172	+ p_dec2ex: PROCESS(rst, clk)
145	173	BEGIN
146	174	IF rst = '1' THEN
147		- r_instr <= (OTHERS => '0');
	175	+ r_reg_s <= (OTHERS => '0');
	176	+ r_reg_t <= (OTHERS => '0');
	177	+ r_reg_d <= (OTHERS => '0');
	178	+ r_imm_a <= (OTHERS => '0');
	179	+ r_imm_16 <= (OTHERS => '0');
	180	+ r_imm_26 <= (OTHERS => '0');
	181	+ r_op <= op_none;
	182	+ r_link <= link_none;
	183	+ r_cmp <= cmp_none;
	184	+ r_alu <= alu_none;
	185	+ r_imm <= imm_none;
148	186	ELSIF rising_edge(clk) THEN
149		- r_instr <= std_logic_vector(unsigned(r_instr) +
150		- to_unsigned(1, 32));
	187	+ r_reg_s <= n_reg_s;
	188	+ r_reg_t <= n_reg_t;
	189	+ r_reg_d <= n_reg_d;
	190	+ r_imm_a <= n_imm_a;
	191	+ r_imm_16 <= n_imm_16;
	192	+ r_imm_26 <= n_imm_26;
	193	+ r_op <= n_op;
	194	+ r_link <= n_link;
	195	+ r_cmp <= n_cmp;
	196	+ r_alu <= n_alu;
	197	+ r_imm <= n_imm;
151	198	END IF;
152		- END PROCESS p_dummy_fetch;
	199	+ END PROCESS p_dec2ex;
153	200
154		- p_alu_in: PROCESS(s_op, s_imm, s_val_s, s_val_t, s_imm_a, s_imm_16)
	201	+ p_alu_in: PROCESS(r_op, r_imm, s_val_s, s_val_t, r_imm_a, r_imm_16)
155	202	BEGIN
156	203	s_alu_op1 <= (OTHERS => '0');
157	204	s_alu_op2 <= (OTHERS => '0');
158		- IF s_op = op_alu THEN
159		- CASE s_imm IS
	205	+ IF r_op = op_alu THEN
	206	+ CASE r_imm IS
160	207	WHEN imm_none =>
161	208	s_alu_op1 <= s_val_s;
162	209	s_alu_op2 <= s_val_t;
163	210	WHEN imm_a =>
164		- s_alu_op1(4 DOWNTO 0) <= s_imm_a;
	211	+ s_alu_op1(4 DOWNTO 0) <= r_imm_a;
165	212	s_alu_op2 <= s_val_t;
166	213	WHEN imm_16se =>
167	214	s_alu_op1 <= s_val_s;
168		- s_alu_op2(15 DOWNTO 0) <= s_imm_16;
169		- IF (s_imm_16(15) = '1') THEN
	215	+ s_alu_op2(15 DOWNTO 0) <= r_imm_16;
	216	+ IF (r_imm_16(15) = '1') THEN
170	217	s_alu_op2(31 DOWNTO 16) <= (OTHERS => '1');
171	218	END IF;
172	219	WHEN imm_16ze =>
173	220	s_alu_op1 <= s_val_s;
174		- s_alu_op2(15 DOWNTO 0) <= s_imm_16;
	221	+ s_alu_op2(15 DOWNTO 0) <= r_imm_16;
175	222	WHEN OTHERS => NULL;
176	223	END CASE;
177	224	END IF;
178	225	END PROCESS p_alu_in;
179	226
180		- p_cmp_in: PROCESS(s_op, s_val_s, s_val_t)
	227	+ p_cmp_in: PROCESS(r_op, s_val_s, s_val_t)
181	228	BEGIN
182	229	s_cmp_op1 <= (OTHERS => '0');
183	230	s_cmp_op2 <= (OTHERS => '0');
184		- IF s_op = op_j THEN
	231	+ IF r_op = op_j THEN
185	232	s_cmp_op1 <= s_val_s;
186	233	s_cmp_op2 <= s_val_t;
187	234	END IF;
188	235	END PROCESS p_cmp_in;
189	236
190		- p_reg_wr: PROCESS(s_op, s_imm, s_reg_t, s_reg_d)
	237	+ p_reg_wr: PROCESS(r_op, r_imm, r_reg_t, r_reg_d)
191	238	BEGIN
192	239	s_reg_wr_no <= (OTHERS => '0');
193	240	s_reg_wr_data <= (OTHERS => '0');
194	241	s_reg_wr_en <= '0';
195		- IF s_op = op_alu THEN
196		- CASE s_imm IS
	242	+ IF r_op = op_alu THEN
	243	+ CASE r_imm IS
197	244	WHEN imm_none \| imm_a =>
198		- s_reg_wr_no <= s_reg_d;
	245	+ s_reg_wr_no <= r_reg_d;
199	246	s_reg_wr_data <= s_alu_res;
200	247	s_reg_wr_en <= '1';
201	248	WHEN imm_16se \| imm_16ze =>
202		- s_reg_wr_no <= s_reg_t;
	249	+ s_reg_wr_no <= r_reg_t;
203	250	s_reg_wr_data <= s_alu_res;
204	251	s_reg_wr_en <= '1';
205	252	WHEN OTHERS => NULL;
...	...	@@ -207,34 +254,21 @@ BEGIN
207	254	END IF;
208	255	END PROCESS p_reg_wr;
209	256
210		- p_next_pc: PROCESS(s_op, s_imm, s_cmp_res, s_imm_16, s_imm_26)
	257	+ p_next_pc: PROCESS(r_pc, r_op, r_imm, s_cmp_res, r_imm_16, r_imm_26)
211	258	VARIABLE v_pc: signed(31 DOWNTO 0);
212	259	VARIABLE v_rel: signed(17 DOWNTO 0);
213	260	BEGIN
214		- -- FIXME
215		- IF s_cmp_res = '1' AND s_imm = imm_26 THEN
216		- n_pc <= r_pc(31 DOWNTO 28) & s_imm_26 & "00";
	261	+ IF r_op = op_j AND s_cmp_res = '1' THEN
	262	+ IF r_imm = imm_26 THEN
	263	+ n_pc <= r_pc(31 DOWNTO 28) & r_imm_26 & "00";
217	264	ELSE
218		- v_pc := signed(r_pc);
219		- v_rel := to_signed(4, 18);
220		- IF s_cmp_res = '1' THEN
221		- v_rel := signed(s_imm_16 & "00");
	265	+ n_pc <= std_logic_vector(signed(r_pc) +
	266	+ signed(r_imm_16 & "00"));
222	267	END IF;
223		- v_pc := v_pc + v_rel;
224		- n_pc <= std_logic_vector(v_pc);
	268	+ ELSE
	269	+ n_pc <= std_logic_vector(signed(r_pc) + to_signed(4, 32));
225	270	END IF;
226	271	END PROCESS p_next_pc;
227	272
228		- p_sync: PROCESS(rst, clk)
229		- BEGIN
230		- IF rst = '1' THEN
231		- r_pc <= (OTHERS => '0');
232		- ELSIF rising_edge(clk) THEN
233		- r_pc <= n_pc;
234		- END IF;
235		- END PROCESS p_sync;
236		-
237		- o_res <= s_alu_res;
238		-
239	273	END ARCHITECTURE a_mips_core;
240	274
241	275