mips_sys

MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Tree: 14cef84dbd46fa0958be3a641af7a6049b681045
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Stefan Schuermans Stefan Schuermans implemented ethernet TX frame generation and register interface (no firmware yet, no simulation testbed support yet, not tested yet) 14cef84 @ 2012-03-05 22:01:56
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eth.vhd implemented ethernet TX frame generation and register interface (no firmware yet, no simulation testbed support yet, not tested yet) 2012-03-05 22:01:56
rst.vhd begin of ethernet RX implementation, so far only test interface to core, does not meet timing 2012-02-20 21:16:03
rxframe.vhd implemented ethernet RX busmaster -> packet reception working 2012-03-03 23:42:55
rxif.vhd begin of ethernet RX implementation, so far only test interface to core, does not meet timing 2012-02-20 21:16:03
txframe.vhd implemented ethernet TX frame generation and register interface (no firmware yet, no simulation testbed support yet, not tested yet) 2012-03-05 22:01:56
txif.vhd implemented ethernet TX interface (not tested yet) 2012-03-04 21:38:35