MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
fixed uninitialized / not resetted frame done output of ethernet TX frame processing
13632e3 @ 2012-03-10 10:56:08
| .. | ||
|---|---|---|
| alu.vhd | added decoding of simple load/store instructions and lui instruction implemented lui instruction fix syntax bug in regs | 2012-01-26 20:50:15 |
| cmp.vhd | if not comparing, jump is unconditional, so compare must return true | 2012-02-10 22:45:59 |
| core.vhd | converted core to use req and grant signals to access data bus | 2012-03-01 21:23:47 |
| decoder.vhd | fixed decoding jump instructions | 2012-02-10 22:45:29 |
| div.vhd | add initial values for registers | 2012-02-12 18:05:38 |
| mul_fast.vhd | add initial values for registers | 2012-02-12 18:05:38 |
| mul_slow.vhd | add initial values for registers | 2012-02-12 18:05:38 |
| regs.vhd | add initial values for registers | 2012-02-12 18:05:38 |
| shifter.vhd | fix unused signals | 2012-02-05 13:21:27 |
| types.vhd | decoding MULT(U)/DIV(U) -> MIPSel1 decoder complete | 2012-02-05 17:32:53 |