mips_sys

1) LIBRARY ieee;
2) USE ieee.std_logic_1164.all;
3) USE ieee.numeric_std.all;
4) USE std.textio.all;

5) USE work.io_lcd_pins.all;

6) USE work.io_switches_pins.all;

7) 
8) ENTITY e_testbed IS
9) END ENTITY e_testbed;
10) 
11) ARCHITECTURE a_testbed OF e_testbed IS
12) 
13)     COMPONENT e_system IS
14)         PORT (

15)             clk:              IN  std_logic;
16)             pin_o_leds:       OUT std_logic_vector(7 DOWNTO 0);
17)             pin_o_lcd:        OUT t_io_lcd_pins;
18)             pin_i_switches:   IN  t_io_switches_pins;
19)             pin_i_uart_rx:    IN  std_logic;
20)             pin_o_uart_tx:    OUT std_logic;
21)             pin_i_eth_rx_clk: IN  std_logic;
22)             pin_i_eth_rxd:    IN  std_logic_vector(4 DOWNTO 0);
23)             pin_i_eth_rx_dv:  IN  std_logic;
24)             pin_i_eth_crs:    IN  std_logic;
25)             pin_i_eth_col:    IN  std_logic;
26)             pin_i_eth_tx_clk: IN  std_logic;
27)             pin_o_eth_txd:    OUT std_logic_vector(3 DOWNTO 0);
28)             pin_o_eth_tx_en:  OUT std_logic

29)         );
30)     END COMPONENT e_system;
31) 

32)     -- ICMP echo request
33)     TYPE t_eth_data IS ARRAY(0 TO 220 - 1) OF std_logic_vector(3 DOWNTO 0);

34)     CONSTANT eth_data: t_eth_data := (
35)         X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5",
36)         X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"D",

37)         X"2", X"0", X"D", X"4", X"9", X"4", X"0", X"5",
38)         X"3", X"5", X"1", X"0", X"0", X"0", X"D", X"1",
39)         X"0", X"6", X"C", X"D", X"5", X"7", X"D", X"2",
40)         X"8", X"0", X"0", X"0", X"5", X"4", X"0", X"0",
41)         X"0", X"0", X"4", X"5", X"0", X"0", X"0", X"0",
42)         X"0", X"4", X"0", X"0", X"0", X"4", X"1", X"0",
43)         X"8", X"B", X"5", X"F", X"0", X"C", X"8", X"A",
44)         X"0", X"0", X"A", X"0", X"0", X"C", X"8", X"A",
45)         X"0", X"0", X"9", X"5", X"8", X"0", X"0", X"0",
46)         X"E", X"8", X"7", X"5", X"F", X"0", X"2", X"6",
47)         X"0", X"0", X"1", X"0", X"6", X"E", X"4", X"B",
48)         X"D", X"6", X"F", X"4", X"0", X"0", X"0", X"0",
49)         X"0", X"0", X"0", X"0", X"4", X"4", X"E", X"6",
50)         X"3", X"0", X"0", X"0", X"0", X"0", X"0", X"0",
51)         X"0", X"0", X"0", X"0", X"0", X"1", X"1", X"1",
52)         X"2", X"1", X"3", X"1", X"4", X"1", X"5", X"1",
53)         X"6", X"1", X"7", X"1", X"8", X"1", X"9", X"1",
54)         X"A", X"1", X"B", X"1", X"C", X"1", X"D", X"1",
55)         X"E", X"1", X"F", X"1", X"0", X"2", X"1", X"2",
56)         X"2", X"2", X"3", X"2", X"4", X"2", X"5", X"2",
57)         X"6", X"2", X"7", X"2", X"8", X"2", X"9", X"2",
58)         X"A", X"2", X"B", X"2", X"C", X"2", X"D", X"2",
59)         X"E", X"2", X"F", X"2", X"0", X"3", X"1", X"3",
60)         X"2", X"3", X"3", X"3", X"4", X"3", X"5", X"3",
61)         X"6", X"3", X"7", X"3", X"2", X"9", X"1", X"C",
62)         X"0", X"1", X"2", X"C"

63)         );
64) 

65)     SIGNAL s_clk:       std_logic;
66)     SIGNAL s_leds:      std_logic_vector(7 DOWNTO 0);
67)     SIGNAL s_lcd:       t_io_lcd_pins;
68)     SIGNAL s_uart:      std_logic;
69)     SIGNAL s_eth_clk:   std_logic;
70)     SIGNAL s_eth_rxd_d: std_logic_vector(3 DOWNTO 0);
71)     SIGNAL s_eth_rxd:   std_logic_vector(4 DOWNTO 0);
72)     SIGNAL s_eth_rx_dv: std_logic;
73)     SIGNAL s_eth_txd:   std_logic_vector(3 DOWNTO 0);
74)     SIGNAL s_eth_tx_en: std_logic;

75) 
76) BEGIN
77) 
78)     system: e_system
79)         PORT MAP (

80)             clk              => s_clk,

81)             pin_o_leds       => s_leds,
82)             pin_o_lcd        => s_lcd,

83)             pin_i_switches   => (sw => (OTHERS => '0'), OTHERS => '0'),

84)             pin_i_uart_rx    => '1',
85)             pin_o_uart_tx    => s_uart,

86)             pin_i_eth_rx_clk => s_eth_clk,

87)             pin_i_eth_rxd    => s_eth_rxd,

88)             pin_i_eth_rx_dv  => s_eth_rx_dv,
89)             pin_i_eth_crs    => s_eth_rx_dv,

90)             pin_i_eth_col    => '0',

91)             pin_i_eth_tx_clk => s_eth_clk,

92)             pin_o_eth_txd    => s_eth_txd,
93)             pin_o_eth_tx_en  => s_eth_tx_en

94)         );
95) 

96)     s_eth_rxd <= "0" & s_eth_rxd_d;

97) 
98)     p_clk: PROCESS

99)     BEGIN
100)         WHILE TRUE LOOP

101)             s_clk <= '0';

102)             WAIT FOR 10 ns;
103)             s_clk <= '1';
104)             WAIT FOR 10 ns;
105)         END LOOP;

106)     END PROCESS p_clk;
107) 
108)     p_eth_clk: PROCESS
109)     BEGIN
110)         WHILE TRUE LOOP
111)             s_eth_clk <= '0';
112)             WAIT FOR 20 ns;
113)             s_eth_clk <= '1';
114)             WAIT FOR 20 ns;
115)         END LOOP;
116)     END PROCESS p_eth_clk;
117) 

118)     p_eth_rx_data: PROCESS

119)     BEGIN

120)         s_eth_rxd_d <= "0000";

121)         s_eth_rx_dv <= '0';

122)         WAIT FOR 25 ms;

123)         WAIT UNTIL s_eth_clk = '1';
124)         WAIT UNTIL s_eth_clk = '0';
125)         FOR i IN 0 TO eth_data'length - 1 LOOP

126)             s_eth_rxd_d <= eth_data(i);

127)             s_eth_rx_dv <= '1';
128)             WAIT UNTIL s_eth_clk = '1';
129)             WAIT UNTIL s_eth_clk = '0';
130)         END LOOP;

131)         s_eth_rxd_d <= "0000";

132)         s_eth_rx_dv <= '0';
133)         WAIT;

134)     END PROCESS p_eth_rx_data;
135) 
136)     p_eth_tx_data: PROCESS
137)         VARIABLE l: line;
138)     BEGIN
139)         FOR i IN 0 TO eth_data'length - 1 LOOP
140)             WAIT UNTIL s_eth_clk = '0';
141)             WAIT UNTIL s_eth_clk = '1';
142)             IF s_eth_tx_en = '1' THEN
143)                 write(l, "ethernet TX: ");
144)                 write(l, to_integer(unsigned(s_eth_txd)));
145)                 writeline(output, l);
146)             END IF;
147)         END LOOP;
148)     END PROCESS p_eth_tx_data;