mips_sys

1) LIBRARY ieee;
2) USE ieee.std_logic_1164.all;
3) USE ieee.numeric_std.all;
4) USE std.textio.all;

5) USE work.io_lcd_pins.all;

6) USE work.io_switches_pins.all;

7) 
8) ENTITY e_testbed IS
9) END ENTITY e_testbed;
10) 
11) ARCHITECTURE a_testbed OF e_testbed IS
12) 
13)     COMPONENT e_system IS
14)         PORT (

15)             clk:              IN  std_logic;
16)             pin_o_leds:       OUT std_logic_vector(7 DOWNTO 0);
17)             pin_o_lcd:        OUT t_io_lcd_pins;
18)             pin_i_switches:   IN  t_io_switches_pins;
19)             pin_i_uart_rx:    IN  std_logic;
20)             pin_o_uart_tx:    OUT std_logic;
21)             pin_i_eth_rx_clk: IN  std_logic;
22)             pin_i_eth_rxd:    IN  std_logic_vector(4 DOWNTO 0);
23)             pin_i_eth_rx_dv:  IN  std_logic;
24)             pin_i_eth_crs:    IN  std_logic;
25)             pin_i_eth_col:    IN  std_logic;
26)             pin_i_eth_tx_clk: IN  std_logic;
27)             pin_o_eth_txd:    OUT std_logic_vector(3 DOWNTO 0);
28)             pin_o_eth_tx_en:  OUT std_logic

29)         );
30)     END COMPONENT e_system;
31) 

32)     TYPE t_eth_data IS ARRAY(0 TO 108 - 1) OF std_logic_vector(3 DOWNTO 0);

33)     CONSTANT eth_data: t_eth_data := (
34)         X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5",
35)         X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"D",
36)         X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"F",

37)         X"F", X"F", X"F", X"F", X"2", X"0", X"3", X"0",
38)         X"4", X"0", X"5", X"0", X"6", X"0", X"7", X"0",
39)         X"8", X"0", X"6", X"0", X"0", X"0", X"1", X"0",
40)         X"8", X"0", X"0", X"0", X"6", X"0", X"4", X"0",
41)         X"0", X"0", X"1", X"0", X"0", X"0", X"d", X"1",
42)         X"0", X"6", X"c", X"d", X"5", X"7", X"d", X"2",
43)         X"0", X"c", X"8", X"a", X"0", X"0", X"a", X"0",
44)         X"f", X"f", X"f", X"f", X"f", X"f", X"f", X"f",
45)         X"f", X"f", X"f", X"f", X"0", X"c", X"8", X"a",
46)         X"0", X"0", X"9", X"5", X"0", X"E", X"8", X"0",
47)         X"8", X"C", X"1", X"B"

48)         );
49) 

50)     SIGNAL s_clk:           std_logic;
51)     SIGNAL s_leds:          std_logic_vector(7 DOWNTO 0);
52)     SIGNAL s_lcd:           t_io_lcd_pins;
53)     SIGNAL s_uart_loopback: std_logic;
54)     SIGNAL s_eth_clk:       std_logic;
55)     SIGNAL s_eth_rxd_d:     std_logic_vector(3 DOWNTO 0);
56)     SIGNAL s_eth_rxd:       std_logic_vector(4 DOWNTO 0);
57)     SIGNAL s_eth_rx_dv:     std_logic;
58)     SIGNAL s_eth_txd:       std_logic_vector(3 DOWNTO 0);
59)     SIGNAL s_eth_tx_en:     std_logic;

60) 
61) BEGIN
62) 
63)     system: e_system
64)         PORT MAP (

65)             clk              => s_clk,

66)             pin_o_leds       => s_leds,
67)             pin_o_lcd        => s_lcd,

68)             pin_i_switches   => (sw => (OTHERS => '0'), OTHERS => '0'),

69)             pin_i_uart_rx    => s_uart_loopback,
70)             pin_o_uart_tx    => s_uart_loopback,

71)             pin_i_eth_rx_clk => s_eth_clk,

72)             pin_i_eth_rxd    => s_eth_rxd,

73)             pin_i_eth_rx_dv  => s_eth_rx_dv,
74)             pin_i_eth_crs    => s_eth_rx_dv,

75)             pin_i_eth_col    => '0',

76)             pin_i_eth_tx_clk => s_eth_clk,

77)             pin_o_eth_txd    => s_eth_txd,
78)             pin_o_eth_tx_en  => s_eth_tx_en

79)         );
80) 

81)     s_eth_rxd <= "0" & s_eth_rxd_d;

82) 
83)     p_clk: PROCESS

84)     BEGIN
85)         WHILE TRUE LOOP

86)             s_clk <= '0';

87)             WAIT FOR 10 ns;
88)             s_clk <= '1';
89)             WAIT FOR 10 ns;
90)         END LOOP;

91)     END PROCESS p_clk;
92) 
93)     p_eth_clk: PROCESS
94)     BEGIN
95)         WHILE TRUE LOOP
96)             s_eth_clk <= '0';
97)             WAIT FOR 20 ns;
98)             s_eth_clk <= '1';
99)             WAIT FOR 20 ns;
100)         END LOOP;
101)     END PROCESS p_eth_clk;
102) 

103)     p_eth_rx_data: PROCESS

104)     BEGIN

105)         s_eth_rxd_d <= "0000";

106)         s_eth_rx_dv <= '0';

107)         WAIT FOR 25 ms;

108)         WAIT UNTIL s_eth_clk = '1';
109)         WAIT UNTIL s_eth_clk = '0';
110)         FOR i IN 0 TO eth_data'length - 1 LOOP

111)             s_eth_rxd_d <= eth_data(i);

112)             s_eth_rx_dv <= '1';
113)             WAIT UNTIL s_eth_clk = '1';
114)             WAIT UNTIL s_eth_clk = '0';
115)         END LOOP;

116)         s_eth_rxd_d <= "0000";

117)         s_eth_rx_dv <= '0';
118)         WAIT;

119)     END PROCESS p_eth_rx_data;
120) 
121)     p_eth_tx_data: PROCESS
122)         VARIABLE l: line;
123)     BEGIN
124)         FOR i IN 0 TO eth_data'length - 1 LOOP
125)             WAIT UNTIL s_eth_clk = '0';
126)             WAIT UNTIL s_eth_clk = '1';
127)             IF s_eth_tx_en = '1' THEN
128)                 write(l, "ethernet TX: ");
129)                 write(l, to_integer(unsigned(s_eth_txd)));
130)                 writeline(output, l);
131)             END IF;
132)         END LOOP;
133)     END PROCESS p_eth_tx_data;