mips_sys

improve synchonous FIFO implementation (get rid of delays between reads)

Stefan Schuermans authored on 2012-03-11 18:59:11

remove leftover comments

Stefan Schuermans authored on 2012-03-11 18:44:23

replaced ethernet RX clock domain crossing interface with dual clock FIFO

Stefan Schuermans authored on 2012-03-10 17:43:57

remove unneeded type definition

Stefan Schuermans authored on 2012-03-10 11:16:40

fixed uninitialized / not resetted frame done output of ethernet TX frame processing

Stefan Schuermans authored on 2012-03-10 10:56:08

added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing

Stefan Schuermans authored on 2012-03-10 10:50:55

send ethernet packet on center button press

Stefan Schuermans authored on 2012-03-07 21:52:08

ethernet TX function takes const pointer

Stefan Schuermans authored on 2012-03-07 21:19:40

adapt ethernet TX clock timing constraint to transmission of data on falling edge

Stefan Schuermans authored on 2012-03-07 21:18:54

fix CRC generation during ethernet transmission trigger CRC generator only once per byte get CRC value _after_ last byte

Stefan Schuermans authored on 2012-03-07 21:15:53