added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing (1f34390) - mips_sys · BlinkenArea

added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing

Stefan Schuermans commited on 2012-03-10 10:50:55
Showing 4 changed files, with 333 additions and 93 deletions.

blocks/fifo_dc.vhd 0000000..20a714a
blocks/rwram_dc.vhd 0000000..404a62b
io/eth/txif.vhd 8e1f417..44627cb
mips_sys.xise 26e5cd7..5e58673

blocks/fifo_dc.vhd

...	...	@@ -0,0 +1,178 @@
	1	+LIBRARY IEEE;
	2	+USE IEEE.STD_LOGIC_1164.ALL;
	3	+USE IEEE.NUMERIC_STD.ALL;
	4	+
	5	+ENTITY e_block_fifo_dc IS
	6	+ GENERIC (
	7	+ addr_width: natural;
	8	+ data_width: natural
	9	+ );
	10	+ PORT (
	11	+ rst: IN std_logic;
	12	+ wr_clk: IN std_logic;
	13	+ o_wr_rdy: OUT std_logic;
	14	+ i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0);
	15	+ i_wr_en: IN std_logic;
	16	+ rd_clk: IN std_logic;
	17	+ o_rd_rdy: OUT std_logic;
	18	+ o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
	19	+ i_rd_en: IN std_logic
	20	+ );
	21	+END ENTITY e_block_fifo_dc;
	22	+
	23	+ARCHITECTURE a_block_fifo_dc OF e_block_fifo_dc IS
	24	+
	25	+ COMPONENT e_block_rwram_dc
	26	+ GENERIC (
	27	+ addr_width: natural;
	28	+ data_width: natural := 8
	29	+ );
	30	+ PORT (
	31	+ rd_clk: IN std_logic;
	32	+ i_rd_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
	33	+ o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
	34	+ wr_clk: IN std_logic;
	35	+ i_wr_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
	36	+ i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0);
	37	+ i_wr_en: IN std_logic
	38	+ );
	39	+ END COMPONENT e_block_rwram_dc;
	40	+
	41	+ SUBTYPE t_pos IS natural RANGE 0 TO 2 ** addr_width - 1;
	42	+ SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
	43	+ SUBTYPE t_data IS std_logic_vector(data_width - 1 DOWNTO 0);
	44	+
	45	+ SIGNAL r_rd_begin: t_pos := 0;
	46	+ SIGNAL n_rd_begin: t_pos;
	47	+ SIGNAL s_rd_begin_addr: t_addr;
	48	+ SIGNAL s_rd_begin_sn_addr: t_addr; -- _sn_ means sometimes next
	49	+ SIGNAL s_rd_rdy: std_logic;
	50	+ SIGNAL s_rd_en: std_logic;
	51	+
	52	+ SIGNAL r_if_begin_addr: t_addr := (OTHERS => '0');
	53	+ SIGNAL r_wr_begin_addr: t_addr := (OTHERS => '0');
	54	+
	55	+ SIGNAL r_wr_end: t_pos := 0;
	56	+ SIGNAL n_wr_end: t_pos;
	57	+ SIGNAL s_wr_end_addr: t_addr;
	58	+ SIGNAL s_wr_end_an_addr: t_addr; -- _an_ means always next
	59	+ SIGNAL s_wr_rdy: std_logic;
	60	+ SIGNAL s_wr_en: std_logic;
	61	+
	62	+ SIGNAL r_if_end_addr: t_addr := (OTHERS => '0');
	63	+ SIGNAL r_rd_end_addr: t_addr := (OTHERS => '0');
	64	+
	65	+ FUNCTION next_pos (
	66	+ pos: natural RANGE 0 TO 2 ** addr_width - 1
	67	+ ) RETURN natural IS
	68	+ VARIABLE v_next: natural RANGE 0 TO 2 ** addr_width - 1;
	69	+ BEGIN
	70	+ IF pos = 2 ** addr_width - 1 THEN
	71	+ v_next := 0;
	72	+ ELSE
	73	+ v_next := pos + 1;
	74	+ END IF;
	75	+ RETURN v_next;
	76	+ END FUNCTION next_pos;
	77	+
	78	+ FUNCTION to_gray (
	79	+ pos: natural RANGE 0 TO 2 ** addr_width - 1
	80	+ ) RETURN std_logic_vector IS
	81	+ VARIABLE v_pos: std_logic_vector(addr_width - 1 DOWNTO 0);
	82	+ VARIABLE v_shifted: std_logic_vector(addr_width - 1 DOWNTO 0);
	83	+ BEGIN
	84	+ v_pos := std_logic_vector(to_unsigned(pos, addr_width));
	85	+ v_shifted := "0" & v_pos(addr_width - 1 DOWNTO 1);
	86	+ RETURN v_pos XOR v_shifted;
	87	+ END FUNCTION to_gray;
	88	+
	89	+BEGIN
	90	+
	91	+ i_rwram: e_block_rwram_dc
	92	+ GENERIC MAP (
	93	+ addr_width => addr_width,
	94	+ data_width => data_width
	95	+ )
	96	+ PORT MAP (
	97	+ rd_clk => rd_clk,
	98	+ i_rd_addr => s_rd_begin_sn_addr,
	99	+ o_rd_data => o_rd_data,
	100	+ wr_clk => wr_clk,
	101	+ i_wr_addr => s_wr_end_addr,
	102	+ i_wr_data => i_wr_data,
	103	+ i_wr_en => s_wr_en
	104	+ );
	105	+
	106	+ s_rd_begin_addr <= to_gray(r_rd_begin);
	107	+ s_rd_begin_sn_addr <= to_gray(n_rd_begin);
	108	+ s_rd_rdy <= '1' WHEN s_rd_begin_addr /= r_rd_end_addr
	109	+ ELSE '0';
	110	+ s_rd_en <= s_rd_rdy AND i_rd_en;
	111	+ o_rd_rdy <= s_rd_rdy;
	112	+
	113	+ p_rd_next: PROCESS(r_rd_begin, s_rd_en)
	114	+ BEGIN
	115	+ n_rd_begin <= r_rd_begin;
	116	+ --n_rd_begin_chg <= false;
	117	+ IF s_rd_en = '1' THEN
	118	+ n_rd_begin <= next_pos(r_rd_begin);
	119	+ --n_rd_begin_chg <= true;
	120	+ END IF;
	121	+ END PROCESS p_rd_next;
	122	+
	123	+ p_rd_sync: PROCESS(rst, rd_clk)
	124	+ BEGIN
	125	+ IF rst = '1' THEN
	126	+ r_rd_begin <= 0;
	127	+ ELSIF rising_edge(rd_clk) THEN
	128	+ r_rd_begin <= n_rd_begin;
	129	+ END IF;
	130	+ END PROCESS p_rd_sync;
	131	+
	132	+ p_rd_if: PROCESS(rst, rd_clk)
	133	+ BEGIN
	134	+ IF rst = '1' THEN
	135	+ r_if_begin_addr <= (OTHERS => '0');
	136	+ r_rd_end_addr <= (OTHERS => '0');
	137	+ ELSIF rising_edge(rd_clk) THEN
	138	+ r_if_begin_addr <= s_rd_begin_addr;
	139	+ r_rd_end_addr <= r_if_end_addr;
	140	+ END IF;
	141	+ END PROCESS p_rd_if;
	142	+
	143	+ s_wr_end_addr <= to_gray(r_wr_end);
	144	+ s_wr_end_an_addr <= to_gray(next_pos(r_wr_end));
	145	+ s_wr_rdy <= '1' WHEN s_wr_end_an_addr /= r_wr_begin_addr ELSE '0';
	146	+ s_wr_en <= s_wr_rdy AND i_wr_en;
	147	+ o_wr_rdy <= s_wr_rdy;
	148	+
	149	+ p_wr_next: PROCESS(r_wr_end, s_wr_en)
	150	+ BEGIN
	151	+ n_wr_end <= r_wr_end;
	152	+ IF s_wr_en = '1' THEN
	153	+ n_wr_end <= next_pos(r_wr_end);
	154	+ END IF;
	155	+ END PROCESS p_wr_next;
	156	+
	157	+ p_wr_sync: PROCESS(rst, wr_clk)
	158	+ BEGIN
	159	+ IF rst = '1' THEN
	160	+ r_wr_end <= 0;
	161	+ ELSIF rising_edge(wr_clk) THEN
	162	+ r_wr_end <= n_wr_end;
	163	+ END IF;
	164	+ END PROCESS p_wr_sync;
	165	+
	166	+ p_wr_if: PROCESS(rst, wr_clk)
	167	+ BEGIN
	168	+ IF rst = '1' THEN
	169	+ r_if_end_addr <= (OTHERS => '0');
	170	+ r_wr_begin_addr <= (OTHERS => '0');
	171	+ ELSIF rising_edge(wr_clk) THEN
	172	+ r_if_end_addr <= s_wr_end_addr;
	173	+ r_wr_begin_addr <= r_if_begin_addr;
	174	+ END IF;
	175	+ END PROCESS p_wr_if;
	176	+
	177	+END ARCHITECTURE a_block_fifo_dc;
	178	+

blocks/rwram_dc.vhd

View file @ 1f34390

...	...	@@ -0,0 +1,50 @@
	1	+LIBRARY IEEE;
	2	+USE IEEE.STD_LOGIC_1164.ALL;
	3	+USE IEEE.NUMERIC_STD.ALL;
	4	+
	5	+-- read write RAM with dual clocks
	6	+
	7	+ENTITY e_block_rwram_dc IS
	8	+ GENERIC (
	9	+ addr_width: natural;
	10	+ data_width: natural
	11	+ );
	12	+ PORT (
	13	+ rd_clk: IN std_logic;
	14	+ i_rd_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
	15	+ o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
	16	+ wr_clk: IN std_logic;
	17	+ i_wr_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
	18	+ i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0);
	19	+ i_wr_en: IN std_logic
	20	+ );
	21	+END ENTITY e_block_rwram_dc;
	22	+
	23	+ARCHITECTURE a_block_rwram_dc OF e_block_rwram_dc IS
	24	+
	25	+ SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
	26	+ SUBTYPE t_data IS std_logic_vector(data_width - 1 DOWNTO 0);
	27	+ TYPE t_buf IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;
	28	+
	29	+ SIGNAL s_buf: t_buf;
	30	+
	31	+BEGIN
	32	+
	33	+ p_rd: PROCESS(rd_clk)
	34	+ BEGIN
	35	+ IF rising_edge(rd_clk) THEN
	36	+ o_rd_data <= s_buf(to_integer(unsigned(i_rd_addr)));
	37	+ END IF;
	38	+ END PROCESS p_rd;
	39	+
	40	+ p_wr: PROCESS(wr_clk)
	41	+ BEGIN
	42	+ IF rising_edge(wr_clk) THEN
	43	+ IF i_wr_en = '1' THEN
	44	+ s_buf(to_integer(unsigned(i_wr_addr))) <= i_wr_data;
	45	+ END IF;
	46	+ END IF;
	47	+ END PROCESS p_wr;
	48	+
	49	+END ARCHITECTURE a_block_rwram_dc;
	50	+

io/eth/txif.vhd

View file @ 1f34390

@@ -22,16 +22,34 @@ ARCHITECTURE a_io_eth_txif OF e_io_eth_txif IS
     TYPE t_in_state IS (in_idle, in_wait);
 
     SIGNAL r_out_state: t_out_state                  := out_idle;
+    SIGNAL n_out_state: t_out_state;
     SIGNAL r_out_data:  std_logic_vector(7 DOWNTO 0) := X"00";
+    SIGNAL n_out_data:  std_logic_vector(7 DOWNTO 0);
 
-    SIGNAL r_if_tx_clk_trigger: std_logic := '0';
-    SIGNAL r_if_tx_clk_detect:  std_logic := '0';
+    SIGNAL s_fifo_wr_rdy:  std_logic;
+    SIGNAL s_fifo_wr_data: std_logic_vector(7 DOWNTO 0);
+    SIGNAL s_fifo_wr_en:   std_logic;
+    SIGNAL s_fifo_rd_rdy:  std_logic;
+    SIGNAL s_fifo_rd_data: std_logic_vector(7 DOWNTO 0);
+    SIGNAL s_fifo_rd_en:   std_logic;
 
-    SIGNAL r_if_clk_data:    std_logic_vector(7 DOWNTO 0) := X"00";
-    SIGNAL r_if_clk_trigger: std_logic                    := '0';
-    SIGNAL r_if_clk_detect:  std_logic                    := '0';
-
-    SIGNAL r_in_state: t_in_state := in_idle;
+    COMPONENT e_block_fifo_dc IS
+        GENERIC (
+            addr_width: natural;
+            data_width: natural
+        );
+        PORT (
+            rst:       IN  std_logic;
+            wr_clk:    IN  std_logic;
+            o_wr_rdy:  OUT std_logic;
+            i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
+            i_wr_en:   IN  std_logic;
+            rd_clk:    IN  std_logic;
+            o_rd_rdy:  OUT std_logic;
+            o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
+            i_rd_en:   IN  std_logic
+        );
+    END COMPONENT e_block_fifo_dc;
 
 BEGIN
 
@@ -56,71 +74,57 @@ BEGIN
         END IF;
     END PROCESS p_out;
 
-    p_if_tx_clk: PROCESS(rst, pin_i_tx_clk)
+    p_out_next: PROCESS(r_out_state, r_out_data, s_fifo_rd_rdy, s_fifo_rd_data)
     BEGIN
-        IF rst = '1' THEN
-            r_out_state         <= out_idle;
-            r_out_data          <= X"00";
-            r_if_tx_clk_trigger <= '0';
-            r_if_tx_clk_detect  <= '0';
-        ELSIF rising_edge(pin_i_tx_clk) THEN
+        n_out_state  <= r_out_state;
+        n_out_data   <= r_out_data;
+        s_fifo_rd_en <= '0';
         CASE r_out_state IS
-                WHEN out_idle =>
-                    IF r_if_clk_trigger /= r_if_tx_clk_detect THEN
-                        r_if_tx_clk_detect  <= NOT r_if_tx_clk_detect;
-                        r_out_state         <= out_data_l;
-                        r_out_data          <= r_if_clk_data;
-                        r_if_tx_clk_trigger <= NOT r_if_tx_clk_trigger;
-                    END IF;
-                WHEN out_data_l =>
-                    r_out_state <= out_data_h;
-                WHEN out_data_h =>
-                    IF r_if_clk_trigger /= r_if_tx_clk_detect THEN
-                        r_if_tx_clk_detect  <= NOT r_if_tx_clk_detect;
-                        r_out_state         <= out_data_l;
-                        r_out_data          <= r_if_clk_data;
-                        r_if_tx_clk_trigger <= NOT r_if_tx_clk_trigger;
+            WHEN out_idle | out_data_h =>
+                IF s_fifo_rd_rdy = '1' THEN
+                    n_out_state  <= out_data_l;
+                    n_out_data   <= s_fifo_rd_data;
+                    s_fifo_rd_en <= '1';
                 ELSE
-                        r_out_state <= out_idle;
+                    n_out_state <= out_idle;
                 END IF;
+            WHEN out_data_l =>
+                n_out_state <= out_data_h;
             WHEN OTHERS => NULL;
         END CASE;
-        END IF;
-    END PROCESS p_if_tx_clk;
+    END PROCESS p_out_next;
 
-    p_if_clk: PROCESS(rst, clk)
+    p_out_sync: PROCESS(rst, pin_i_tx_clk)
     BEGIN
         IF rst = '1' THEN
-            r_if_clk_data    <= X"00";
-            r_if_clk_trigger <= '0';
-            r_if_clk_detect  <= '0';
-            r_in_state       <= in_idle;
-            o_data_ack       <= '0';
-        ELSIF rising_edge(clk) THEN
-            o_data_ack       <= '0';
-            CASE r_in_state IS
-                WHEN in_idle =>
-                    IF i_data_en = '1' THEN
-                        r_if_clk_data    <= i_data;
-                        r_if_clk_trigger <= NOT r_if_clk_trigger;
-                        o_data_ack       <= '1';
-                        r_in_state       <= in_wait;
-                    END IF;
-                WHEN in_wait =>
-                    IF r_if_tx_clk_trigger /= r_if_clk_detect THEN
-                        r_if_clk_detect <= NOT r_if_clk_detect;
-                        IF i_data_en = '1' THEN
-                            r_if_clk_data    <= i_data;
-                            r_if_clk_trigger <= NOT r_if_clk_trigger;
-                            o_data_ack       <= '1';
-                        ELSE
-                            r_in_state <= in_idle;
-                        END IF;
-                    END IF;
-                WHEN OTHERS => NULL;
-            END CASE;
+            r_out_state <= out_idle;
+            r_out_data  <= X"00";
+        ELSIF rising_edge(pin_i_tx_clk) THEN
+            r_out_state <= n_out_state;
+            r_out_data  <= n_out_data;
         END IF;
-    END PROCESS p_if_clk;
+    END PROCESS p_out_sync;
+
+    fifo: e_block_fifo_dc
+        GENERIC MAP (
+            addr_width => 4,
+            data_width => 8
+        )
+        PORT MAP (
+            rst       => rst,
+            wr_clk    => clk,
+            o_wr_rdy  => s_fifo_wr_rdy,
+            i_wr_data => s_fifo_wr_data,
+            i_wr_en   => s_fifo_wr_en,
+            rd_clk    => pin_i_tx_clk,
+            o_rd_rdy  => s_fifo_rd_rdy,
+            o_rd_data => s_fifo_rd_data,
+            i_rd_en   => s_fifo_rd_en
+        );
+
+    s_fifo_wr_data <= i_data;
+    s_fifo_wr_en   <= s_fifo_wr_rdy AND i_data_en;
+    o_data_ack     <= s_fifo_wr_en;    
 
 END ARCHITECTURE a_io_eth_txif;
 

mips_sys.xise

View file @ 1f34390

@@ -16,7 +16,7 @@
 
   <files>
     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
@@ -24,49 +24,49 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
     </file>
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
     </file>
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     </file>
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     </file>
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
@@ -76,93 +76,101 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     </file>
     <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     </file>
     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
     </file>
     <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
     </file>
     <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
     </file>
     <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     </file>
     <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
     <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     </file>
     <file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
     <file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="blocks/crc32.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="io/eth/txif.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="io/eth/txframe.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
+    <file xil_pn:name="blocks/rwram_dc.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
+    </file>
+    <file xil_pn:name="blocks/fifo_dc.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
+    </file>
   </files>
 
   <properties>


...	...	@@ -22,16 +22,34 @@ ARCHITECTURE a_io_eth_txif OF e_io_eth_txif IS
22	22	TYPE t_in_state IS (in_idle, in_wait);
23	23
24	24	SIGNAL r_out_state: t_out_state := out_idle;
	25	+ SIGNAL n_out_state: t_out_state;
25	26	SIGNAL r_out_data: std_logic_vector(7 DOWNTO 0) := X"00";
	27	+ SIGNAL n_out_data: std_logic_vector(7 DOWNTO 0);
26	28
27		- SIGNAL r_if_tx_clk_trigger: std_logic := '0';
28		- SIGNAL r_if_tx_clk_detect: std_logic := '0';
	29	+ SIGNAL s_fifo_wr_rdy: std_logic;
	30	+ SIGNAL s_fifo_wr_data: std_logic_vector(7 DOWNTO 0);
	31	+ SIGNAL s_fifo_wr_en: std_logic;
	32	+ SIGNAL s_fifo_rd_rdy: std_logic;
	33	+ SIGNAL s_fifo_rd_data: std_logic_vector(7 DOWNTO 0);
	34	+ SIGNAL s_fifo_rd_en: std_logic;
29	35
30		- SIGNAL r_if_clk_data: std_logic_vector(7 DOWNTO 0) := X"00";
31		- SIGNAL r_if_clk_trigger: std_logic := '0';
32		- SIGNAL r_if_clk_detect: std_logic := '0';
33		-
34		- SIGNAL r_in_state: t_in_state := in_idle;
	36	+ COMPONENT e_block_fifo_dc IS
	37	+ GENERIC (
	38	+ addr_width: natural;
	39	+ data_width: natural
	40	+ );
	41	+ PORT (
	42	+ rst: IN std_logic;
	43	+ wr_clk: IN std_logic;
	44	+ o_wr_rdy: OUT std_logic;
	45	+ i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0);
	46	+ i_wr_en: IN std_logic;
	47	+ rd_clk: IN std_logic;
	48	+ o_rd_rdy: OUT std_logic;
	49	+ o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
	50	+ i_rd_en: IN std_logic
	51	+ );
	52	+ END COMPONENT e_block_fifo_dc;
35	53
36	54	BEGIN
37	55
...	...	@@ -56,71 +74,57 @@ BEGIN
56	74	END IF;
57	75	END PROCESS p_out;
58	76
59		- p_if_tx_clk: PROCESS(rst, pin_i_tx_clk)
	77	+ p_out_next: PROCESS(r_out_state, r_out_data, s_fifo_rd_rdy, s_fifo_rd_data)
60	78	BEGIN
61		- IF rst = '1' THEN
62		- r_out_state <= out_idle;
63		- r_out_data <= X"00";
64		- r_if_tx_clk_trigger <= '0';
65		- r_if_tx_clk_detect <= '0';
66		- ELSIF rising_edge(pin_i_tx_clk) THEN
	79	+ n_out_state <= r_out_state;
	80	+ n_out_data <= r_out_data;
	81	+ s_fifo_rd_en <= '0';
67	82	CASE r_out_state IS
68		- WHEN out_idle =>
69		- IF r_if_clk_trigger /= r_if_tx_clk_detect THEN
70		- r_if_tx_clk_detect <= NOT r_if_tx_clk_detect;
71		- r_out_state <= out_data_l;
72		- r_out_data <= r_if_clk_data;
73		- r_if_tx_clk_trigger <= NOT r_if_tx_clk_trigger;
74		- END IF;
75		- WHEN out_data_l =>
76		- r_out_state <= out_data_h;
77		- WHEN out_data_h =>
78		- IF r_if_clk_trigger /= r_if_tx_clk_detect THEN
79		- r_if_tx_clk_detect <= NOT r_if_tx_clk_detect;
80		- r_out_state <= out_data_l;
81		- r_out_data <= r_if_clk_data;
82		- r_if_tx_clk_trigger <= NOT r_if_tx_clk_trigger;
	83	+ WHEN out_idle \| out_data_h =>
	84	+ IF s_fifo_rd_rdy = '1' THEN
	85	+ n_out_state <= out_data_l;
	86	+ n_out_data <= s_fifo_rd_data;
	87	+ s_fifo_rd_en <= '1';
83	88	ELSE
84		- r_out_state <= out_idle;
	89	+ n_out_state <= out_idle;
85	90	END IF;
	91	+ WHEN out_data_l =>
	92	+ n_out_state <= out_data_h;
86	93	WHEN OTHERS => NULL;
87	94	END CASE;
88		- END IF;
89		- END PROCESS p_if_tx_clk;
	95	+ END PROCESS p_out_next;
90	96
91		- p_if_clk: PROCESS(rst, clk)
	97	+ p_out_sync: PROCESS(rst, pin_i_tx_clk)
92	98	BEGIN
93	99	IF rst = '1' THEN
94		- r_if_clk_data <= X"00";
95		- r_if_clk_trigger <= '0';
96		- r_if_clk_detect <= '0';
97		- r_in_state <= in_idle;
98		- o_data_ack <= '0';
99		- ELSIF rising_edge(clk) THEN
100		- o_data_ack <= '0';
101		- CASE r_in_state IS
102		- WHEN in_idle =>
103		- IF i_data_en = '1' THEN
104		- r_if_clk_data <= i_data;
105		- r_if_clk_trigger <= NOT r_if_clk_trigger;
106		- o_data_ack <= '1';
107		- r_in_state <= in_wait;
108		- END IF;
109		- WHEN in_wait =>
110		- IF r_if_tx_clk_trigger /= r_if_clk_detect THEN
111		- r_if_clk_detect <= NOT r_if_clk_detect;
112		- IF i_data_en = '1' THEN
113		- r_if_clk_data <= i_data;
114		- r_if_clk_trigger <= NOT r_if_clk_trigger;
115		- o_data_ack <= '1';
116		- ELSE
117		- r_in_state <= in_idle;
118		- END IF;
119		- END IF;
120		- WHEN OTHERS => NULL;
121		- END CASE;
	100	+ r_out_state <= out_idle;
	101	+ r_out_data <= X"00";
	102	+ ELSIF rising_edge(pin_i_tx_clk) THEN
	103	+ r_out_state <= n_out_state;
	104	+ r_out_data <= n_out_data;
122	105	END IF;
123		- END PROCESS p_if_clk;
	106	+ END PROCESS p_out_sync;
	107	+
	108	+ fifo: e_block_fifo_dc
	109	+ GENERIC MAP (
	110	+ addr_width => 4,
	111	+ data_width => 8
	112	+ )
	113	+ PORT MAP (
	114	+ rst => rst,
	115	+ wr_clk => clk,
	116	+ o_wr_rdy => s_fifo_wr_rdy,
	117	+ i_wr_data => s_fifo_wr_data,
	118	+ i_wr_en => s_fifo_wr_en,
	119	+ rd_clk => pin_i_tx_clk,
	120	+ o_rd_rdy => s_fifo_rd_rdy,
	121	+ o_rd_data => s_fifo_rd_data,
	122	+ i_rd_en => s_fifo_rd_en
	123	+ );
	124	+
	125	+ s_fifo_wr_data <= i_data;
	126	+ s_fifo_wr_en <= s_fifo_wr_rdy AND i_data_en;
	127	+ o_data_ack <= s_fifo_wr_en;
124	128
125	129	END ARCHITECTURE a_io_eth_txif;
126	130

...	...	@@ -16,7 +16,7 @@
16	16
17	17	<files>
18	18	<file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
19		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
	19	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
20	20	<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
21	21	</file>
22	22	<file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
...	...	@@ -24,49 +24,49 @@
24	24	<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
25	25	</file>
26	26	<file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
27		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
	27	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
28	28	<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
	31	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
32	32	<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
33	33	</file>
34	34	<file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
35		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
	35	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
36	36	<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
37	37	</file>
38	38	<file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
39		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
	39	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
40	40	<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
41	41	</file>
42	42	<file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
43		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
	43	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
44	44	<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
45	45	</file>
46	46	<file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
47		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
	47	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
48	48	<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
49	49	</file>
50	50	<file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
51		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
	51	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
52	52	<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
53	53	</file>
54	54	<file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
55		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
	55	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
56	56	<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
57	57	</file>
58	58	<file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
59		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
	59	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
60	60	<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
61	61	<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
62	62	<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
63	63	</file>
64	64	<file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
65		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
	65	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
66	66	<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
67	67	</file>
68	68	<file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
69		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
	69	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
70	70	<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
71	71	</file>
72	72	<file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
...	...	@@ -76,93 +76,101 @@
76	76	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
77	77	</file>
78	78	<file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
79		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
	79	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
80	80	<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
81	81	</file>
82	82	<file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
83		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
	83	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
84	84	<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
85	85	</file>
86	86	<file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
87		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
	87	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
88	88	<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
89	89	</file>
90	90	<file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
91	91	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
92	92	</file>
93	93	<file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
94		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
	94	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
95	95	<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
96	96	</file>
97	97	<file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
98		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
	98	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
99	99	<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
100	100	</file>
101	101	<file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
102		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
	102	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
103	103	<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
104	104	</file>
105	105	<file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
106		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
	106	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
107	107	<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
108	108	</file>
109	109	<file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
110		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
	110	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
111	111	<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
112	112	</file>
113	113	<file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
114		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
	114	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
115	115	<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
116	116	</file>
117	117	<file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
118	118	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
119	119	</file>
120	120	<file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
121		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
	121	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
122	122	<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
123	123	</file>
124	124	<file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
125	125	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
126	126	</file>
127	127	<file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
128		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
	128	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
129	129	<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
130	130	</file>
131	131	<file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
132		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
	132	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
133	133	<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
134	134	</file>
135	135	<file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
136		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
	136	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
137	137	<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
138	138	</file>
139	139	<file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
140		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
	140	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
141	141	<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
142	142	</file>
143	143	<file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">
144		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
	144	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
145	145	<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
146	146	</file>
147	147	<file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF">
148	148	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
149	149	</file>
150	150	<file xil_pn:name="blocks/crc32.vhd" xil_pn:type="FILE_VHDL">
151		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
	151	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
152	152	<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
153	153	</file>
154	154	<file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">
155		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
	155	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
156	156	<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
157	157	</file>
158	158	<file xil_pn:name="io/eth/txif.vhd" xil_pn:type="FILE_VHDL">
159		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
	159	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
160	160	<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
161	161	</file>
162	162	<file xil_pn:name="io/eth/txframe.vhd" xil_pn:type="FILE_VHDL">
163		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
	163	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
164	164	<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
165	165	</file>
	166	+ <file xil_pn:name="blocks/rwram_dc.vhd" xil_pn:type="FILE_VHDL">
	167	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
	168	+ <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
	169	+ </file>
	170	+ <file xil_pn:name="blocks/fifo_dc.vhd" xil_pn:type="FILE_VHDL">
	171	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
	172	+ <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
	173	+ </file>
166	174	</files>
167	175
168	176	<properties>
169	177