replaced ethernet RX clock domain crossing interface with dual clock FIFO (7ea541c) - mips_sys · BlinkenArea

io/eth/rxif.vhd

@@ -26,21 +26,29 @@ ARCHITECTURE a_io_eth_rxif OF e_io_eth_rxif IS
     SIGNAL r_in_state: t_in_state                   := in_idle;
     SIGNAL r_in_data:  std_logic_vector(7 DOWNTO 0) := X"00";
 
-    TYPE t_if_event IS (if_data, if_done, if_err);
-
-    SIGNAL r_if_rx_clk_trigger: std_logic                    := '0';
-    SIGNAL r_if_rx_clk_event:   t_if_event                   := if_data;
-    SIGNAL r_if_rx_clk_data:    std_logic_vector(7 DOWNTO 0) := X"00";
-
-    SIGNAL r_if_clk_trigger: std_logic                    := '0';
-    SIGNAL r_if_clk_event:   t_if_event                   := if_data;
-    SIGNAL r_if_clk_data:    std_logic_vector(7 DOWNTO 0) := X"00";
-    SIGNAL r_if_clk_en:      std_logic                    := '0';
-
-    SIGNAL r_out_data:    std_logic_vector(7 DOWNTO 0) := X"00";
-    SIGNAL r_out_data_en: std_logic                    := '0';
-    SIGNAL r_out_done:    std_logic                    := '0';
-    SIGNAL r_out_err:     std_logic                    := '0';
+    SIGNAL s_fifo_wr_rdy:  std_logic;
+    SIGNAL s_fifo_wr_data: std_logic_vector(9 DOWNTO 0);
+    SIGNAL s_fifo_wr_en:   std_logic;
+    SIGNAL s_fifo_rd_rdy:  std_logic;
+    SIGNAL s_fifo_rd_data: std_logic_vector(9 DOWNTO 0);
+
+    COMPONENT e_block_fifo_dc IS
+        GENERIC (
+            addr_width: natural;
+            data_width: natural
+        );
+        PORT (
+            rst:       IN  std_logic;
+            wr_clk:    IN  std_logic;
+            o_wr_rdy:  OUT std_logic;
+            i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
+            i_wr_en:   IN  std_logic;
+            rd_clk:    IN  std_logic;
+            o_rd_rdy:  OUT std_logic;
+            o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
+            i_rd_en:   IN  std_logic
+        );
+    END COMPONENT e_block_fifo_dc;
 
 BEGIN
 
@@ -114,79 +122,47 @@ BEGIN
         END IF;
     END PROCESS p_in;
 
-    p_if_rx_clk: PROCESS(rst, pin_i_rx_clk)
+    p_wr_fifo: PROCESS(r_in_state, r_in_data, s_fifo_wr_rdy)
     BEGIN
-        IF rst = '1' THEN
-            r_if_rx_clk_trigger <= '0';
-            r_if_rx_clk_event   <= if_data;
-            r_if_rx_clk_data    <= X"00";
-        ELSIF rising_edge(pin_i_rx_clk) THEN
+        s_fifo_wr_data <= (OTHERS => '0');
+        s_fifo_wr_en   <= '0';
+        IF s_fifo_wr_rdy = '1' THEN
             CASE r_in_state IS
                 WHEN in_data =>
-                    r_if_rx_clk_trigger <= NOT r_if_rx_clk_trigger;
-                    r_if_rx_clk_event   <= if_data;
-                    r_if_rx_clk_data    <= r_in_data;
+                    s_fifo_wr_data(7 DOWNTO 0) <= r_in_data;
+                    s_fifo_wr_en               <= '1';
                 WHEN in_done =>
-                    r_if_rx_clk_trigger <= NOT r_if_rx_clk_trigger;
-                    r_if_rx_clk_event   <= if_done;
+                    s_fifo_wr_data(8) <= '1';
+                    s_fifo_wr_en      <= '1';
                 WHEN in_err =>
-                    r_if_rx_clk_trigger <= NOT r_if_rx_clk_trigger;
-                    r_if_rx_clk_event   <= if_err;
+                    s_fifo_wr_data(9) <= '1';
+                    s_fifo_wr_en      <= '1';
                 WHEN OTHERS => NULL;
             END CASE;
         END IF;
-    END PROCESS p_if_rx_clk;
-
-    p_if_clk: PROCESS(rst, clk)
-    BEGIN
-        IF rst = '1' THEN
-            r_if_clk_trigger <= '0';
-            r_if_clk_event   <= if_data;
-            r_if_clk_data    <= X"00";
-            r_if_clk_en      <= '0';
-        ELSIF rising_edge(clk) THEN
-            IF r_if_rx_clk_trigger /= r_if_clk_trigger THEN
-                r_if_clk_trigger <= NOT r_if_clk_trigger;
-                r_if_clk_event   <= r_if_rx_clk_event;
-                r_if_clk_data    <= r_if_rx_clk_data;
-                r_if_clk_en      <= '1';
-            ELSE
-                r_if_clk_en      <= '0';
-            END IF;
-        END IF;
-    END PROCESS p_if_clk;
-
-    p_out: PROCESS(rst, clk)
-    BEGIN
-        IF rst = '1' THEN
-            r_out_data    <= X"00";
-            r_out_data_en <= '0';
-            r_out_done    <= '0';
-            r_out_err     <= '0';
-        ELSIF rising_edge(clk) THEN
-            r_out_data    <= X"00";
-            r_out_data_en <= '0';
-            r_out_done    <= '0';
-            r_out_err     <= '0';
-            IF r_if_clk_en = '1' THEN
-                CASE r_if_clk_event IS
-                    WHEN if_data =>
-                        r_out_data    <= r_if_clk_data;
-                        r_out_data_en <= '1';
-                    WHEN if_done =>
-                        r_out_done    <= '1';
-                    WHEN if_err =>
-                        r_out_err     <= '1';
-                    WHEN OTHERS => NULL;
-                END CASE;
-            END IF;
-        END IF;
-    END PROCESS p_out;
+    END PROCESS p_wr_fifo;
+
+    fifo: e_block_fifo_dc
+        GENERIC MAP (
+            addr_width => 2,
+            data_width => 10
+        )
+        PORT MAP (
+            rst       => rst,
+            wr_clk    => pin_i_rx_clk,
+            o_wr_rdy  => s_fifo_wr_rdy,
+            i_wr_data => s_fifo_wr_data,
+            i_wr_en   => s_fifo_wr_en,
+            rd_clk    => clk,
+            o_rd_rdy  => s_fifo_rd_rdy,
+            o_rd_data => s_fifo_rd_data,
+            i_rd_en   => s_fifo_rd_rdy
+        );
 
-    o_data    <= r_out_data;
-    o_data_en <= r_out_data_en;
-    o_done    <= r_out_done;
-    o_err     <= r_out_err;
+    o_data    <= s_fifo_rd_data(7 DOWNTO 0);
+    o_data_en <= s_fifo_rd_rdy;
+    o_done    <= s_fifo_rd_data(8);
+    o_err     <= s_fifo_rd_data(9);
 
 END ARCHITECTURE a_io_eth_rxif;
 


...	...	@@ -44,6 +44,7 @@
44	44	<wvobject fp_name="/e_testbed/system/pin_i_eth_rxd" type="array" db_ref_id="1">
45	45	<obj_property name="ElementShortName">pin_i_eth_rxd[4:0]</obj_property>
46	46	<obj_property name="ObjectShortName">pin_i_eth_rxd[4:0]</obj_property>
	47	+ <obj_property name="Radix">HEXRADIX</obj_property>
47	48	</wvobject>
48	49	<wvobject fp_name="/e_testbed/system/pin_i_eth_rx_dv" type="logic" db_ref_id="1">
49	50	<obj_property name="ElementShortName">pin_i_eth_rx_dv</obj_property>

...	...	@@ -26,21 +26,29 @@ ARCHITECTURE a_io_eth_rxif OF e_io_eth_rxif IS
26	26	SIGNAL r_in_state: t_in_state := in_idle;
27	27	SIGNAL r_in_data: std_logic_vector(7 DOWNTO 0) := X"00";
28	28
29		- TYPE t_if_event IS (if_data, if_done, if_err);
30		-
31		- SIGNAL r_if_rx_clk_trigger: std_logic := '0';
32		- SIGNAL r_if_rx_clk_event: t_if_event := if_data;
33		- SIGNAL r_if_rx_clk_data: std_logic_vector(7 DOWNTO 0) := X"00";
34		-
35		- SIGNAL r_if_clk_trigger: std_logic := '0';
36		- SIGNAL r_if_clk_event: t_if_event := if_data;
37		- SIGNAL r_if_clk_data: std_logic_vector(7 DOWNTO 0) := X"00";
38		- SIGNAL r_if_clk_en: std_logic := '0';
39		-
40		- SIGNAL r_out_data: std_logic_vector(7 DOWNTO 0) := X"00";
41		- SIGNAL r_out_data_en: std_logic := '0';
42		- SIGNAL r_out_done: std_logic := '0';
43		- SIGNAL r_out_err: std_logic := '0';
	29	+ SIGNAL s_fifo_wr_rdy: std_logic;
	30	+ SIGNAL s_fifo_wr_data: std_logic_vector(9 DOWNTO 0);
	31	+ SIGNAL s_fifo_wr_en: std_logic;
	32	+ SIGNAL s_fifo_rd_rdy: std_logic;
	33	+ SIGNAL s_fifo_rd_data: std_logic_vector(9 DOWNTO 0);
	34	+
	35	+ COMPONENT e_block_fifo_dc IS
	36	+ GENERIC (
	37	+ addr_width: natural;
	38	+ data_width: natural
	39	+ );
	40	+ PORT (
	41	+ rst: IN std_logic;
	42	+ wr_clk: IN std_logic;
	43	+ o_wr_rdy: OUT std_logic;
	44	+ i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0);
	45	+ i_wr_en: IN std_logic;
	46	+ rd_clk: IN std_logic;
	47	+ o_rd_rdy: OUT std_logic;
	48	+ o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
	49	+ i_rd_en: IN std_logic
	50	+ );
	51	+ END COMPONENT e_block_fifo_dc;
44	52
45	53	BEGIN
46	54
...	...	@@ -114,79 +122,47 @@ BEGIN
114	122	END IF;
115	123	END PROCESS p_in;
116	124
117		- p_if_rx_clk: PROCESS(rst, pin_i_rx_clk)
	125	+ p_wr_fifo: PROCESS(r_in_state, r_in_data, s_fifo_wr_rdy)
118	126	BEGIN
119		- IF rst = '1' THEN
120		- r_if_rx_clk_trigger <= '0';
121		- r_if_rx_clk_event <= if_data;
122		- r_if_rx_clk_data <= X"00";
123		- ELSIF rising_edge(pin_i_rx_clk) THEN
	127	+ s_fifo_wr_data <= (OTHERS => '0');
	128	+ s_fifo_wr_en <= '0';
	129	+ IF s_fifo_wr_rdy = '1' THEN
124	130	CASE r_in_state IS
125	131	WHEN in_data =>
126		- r_if_rx_clk_trigger <= NOT r_if_rx_clk_trigger;
127		- r_if_rx_clk_event <= if_data;
128		- r_if_rx_clk_data <= r_in_data;
	132	+ s_fifo_wr_data(7 DOWNTO 0) <= r_in_data;
	133	+ s_fifo_wr_en <= '1';
129	134	WHEN in_done =>
130		- r_if_rx_clk_trigger <= NOT r_if_rx_clk_trigger;
131		- r_if_rx_clk_event <= if_done;
	135	+ s_fifo_wr_data(8) <= '1';
	136	+ s_fifo_wr_en <= '1';
132	137	WHEN in_err =>
133		- r_if_rx_clk_trigger <= NOT r_if_rx_clk_trigger;
134		- r_if_rx_clk_event <= if_err;
	138	+ s_fifo_wr_data(9) <= '1';
	139	+ s_fifo_wr_en <= '1';
135	140	WHEN OTHERS => NULL;
136	141	END CASE;
137	142	END IF;
138		- END PROCESS p_if_rx_clk;
139		-
140		- p_if_clk: PROCESS(rst, clk)
141		- BEGIN
142		- IF rst = '1' THEN
143		- r_if_clk_trigger <= '0';
144		- r_if_clk_event <= if_data;
145		- r_if_clk_data <= X"00";
146		- r_if_clk_en <= '0';
147		- ELSIF rising_edge(clk) THEN
148		- IF r_if_rx_clk_trigger /= r_if_clk_trigger THEN
149		- r_if_clk_trigger <= NOT r_if_clk_trigger;
150		- r_if_clk_event <= r_if_rx_clk_event;
151		- r_if_clk_data <= r_if_rx_clk_data;
152		- r_if_clk_en <= '1';
153		- ELSE
154		- r_if_clk_en <= '0';
155		- END IF;
156		- END IF;
157		- END PROCESS p_if_clk;
158		-
159		- p_out: PROCESS(rst, clk)
160		- BEGIN
161		- IF rst = '1' THEN
162		- r_out_data <= X"00";
163		- r_out_data_en <= '0';
164		- r_out_done <= '0';
165		- r_out_err <= '0';
166		- ELSIF rising_edge(clk) THEN
167		- r_out_data <= X"00";
168		- r_out_data_en <= '0';
169		- r_out_done <= '0';
170		- r_out_err <= '0';
171		- IF r_if_clk_en = '1' THEN
172		- CASE r_if_clk_event IS
173		- WHEN if_data =>
174		- r_out_data <= r_if_clk_data;
175		- r_out_data_en <= '1';
176		- WHEN if_done =>
177		- r_out_done <= '1';
178		- WHEN if_err =>
179		- r_out_err <= '1';
180		- WHEN OTHERS => NULL;
181		- END CASE;
182		- END IF;
183		- END IF;
184		- END PROCESS p_out;
	143	+ END PROCESS p_wr_fifo;
	144	+
	145	+ fifo: e_block_fifo_dc
	146	+ GENERIC MAP (
	147	+ addr_width => 2,
	148	+ data_width => 10
	149	+ )
	150	+ PORT MAP (
	151	+ rst => rst,
	152	+ wr_clk => pin_i_rx_clk,
	153	+ o_wr_rdy => s_fifo_wr_rdy,
	154	+ i_wr_data => s_fifo_wr_data,
	155	+ i_wr_en => s_fifo_wr_en,
	156	+ rd_clk => clk,
	157	+ o_rd_rdy => s_fifo_rd_rdy,
	158	+ o_rd_data => s_fifo_rd_data,
	159	+ i_rd_en => s_fifo_rd_rdy
	160	+ );
185	161
186		- o_data <= r_out_data;
187		- o_data_en <= r_out_data_en;
188		- o_done <= r_out_done;
189		- o_err <= r_out_err;
	162	+ o_data <= s_fifo_rd_data(7 DOWNTO 0);
	163	+ o_data_en <= s_fifo_rd_rdy;
	164	+ o_done <= s_fifo_rd_data(8);
	165	+ o_err <= s_fifo_rd_data(9);
190	166
191	167	END ARCHITECTURE a_io_eth_rxif;
192	168
193	169