mips_sys

1) -- MIPS I system
2) -- Copyright 2011-2012 Stefan Schuermans <stefan@schuermans.info>
3) -- Copyleft GNU public license V2 or later
4) --          http://www.gnu.org/copyleft/gpl.html
5) 

6) LIBRARY ieee;
7) USE ieee.std_logic_1164.all;
8) USE ieee.numeric_std.all;
9) USE std.textio.all;

10) USE work.io_eth_pins.all;

11) USE work.io_lcd_pins.all;

12) USE work.io_switches_pins.all;

13) 
14) ENTITY e_testbed IS
15) END ENTITY e_testbed;
16) 
17) ARCHITECTURE a_testbed OF e_testbed IS
18) 
19)     COMPONENT e_system IS
20)         PORT (

21)             clk:            IN  std_logic;
22)             pin_o_leds:     OUT std_logic_vector(7 DOWNTO 0);
23)             pin_o_lcd:      OUT t_io_lcd_pins;
24)             pin_i_switches: IN  t_io_switches_pins;
25)             pin_i_uart_rx:  IN  std_logic;
26)             pin_o_uart_tx:  OUT std_logic;
27)             pin_o_eth:      OUT t_io_eth_o_pins;
28)             pin_i_eth:      IN  t_io_eth_i_pins

29)         );
30)     END COMPONENT e_system;
31) 

32)     -- ICMP echo request
33)     TYPE t_eth_data IS ARRAY(0 TO 220 - 1) OF std_logic_vector(3 DOWNTO 0);

34)     CONSTANT eth_data: t_eth_data := (
35)         X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5",
36)         X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"D",

37)         X"2", X"0", X"D", X"4", X"9", X"4", X"0", X"5",
38)         X"3", X"5", X"1", X"0", X"0", X"0", X"D", X"1",
39)         X"0", X"6", X"C", X"D", X"5", X"7", X"D", X"2",
40)         X"8", X"0", X"0", X"0", X"5", X"4", X"0", X"0",
41)         X"0", X"0", X"4", X"5", X"0", X"0", X"0", X"0",
42)         X"0", X"4", X"0", X"0", X"0", X"4", X"1", X"0",
43)         X"8", X"B", X"5", X"F", X"0", X"C", X"8", X"A",
44)         X"0", X"0", X"A", X"0", X"0", X"C", X"8", X"A",
45)         X"0", X"0", X"9", X"5", X"8", X"0", X"0", X"0",
46)         X"E", X"8", X"7", X"5", X"F", X"0", X"2", X"6",
47)         X"0", X"0", X"1", X"0", X"6", X"E", X"4", X"B",
48)         X"D", X"6", X"F", X"4", X"0", X"0", X"0", X"0",
49)         X"0", X"0", X"0", X"0", X"4", X"4", X"E", X"6",
50)         X"3", X"0", X"0", X"0", X"0", X"0", X"0", X"0",
51)         X"0", X"0", X"0", X"0", X"0", X"1", X"1", X"1",
52)         X"2", X"1", X"3", X"1", X"4", X"1", X"5", X"1",
53)         X"6", X"1", X"7", X"1", X"8", X"1", X"9", X"1",
54)         X"A", X"1", X"B", X"1", X"C", X"1", X"D", X"1",
55)         X"E", X"1", X"F", X"1", X"0", X"2", X"1", X"2",
56)         X"2", X"2", X"3", X"2", X"4", X"2", X"5", X"2",
57)         X"6", X"2", X"7", X"2", X"8", X"2", X"9", X"2",
58)         X"A", X"2", X"B", X"2", X"C", X"2", X"D", X"2",
59)         X"E", X"2", X"F", X"2", X"0", X"3", X"1", X"3",
60)         X"2", X"3", X"3", X"3", X"4", X"3", X"5", X"3",
61)         X"6", X"3", X"7", X"3", X"2", X"9", X"1", X"C",
62)         X"0", X"1", X"2", X"C"

63)         );
64) 

65)     SIGNAL s_clk:       std_logic;
66)     SIGNAL s_leds:      std_logic_vector(7 DOWNTO 0);
67)     SIGNAL s_lcd:       t_io_lcd_pins;
68)     SIGNAL s_uart:      std_logic;

69)     SIGNAL s_o_eth:     t_io_eth_o_pins;
70)     SIGNAL s_i_eth:     t_io_eth_i_pins;

71)     SIGNAL s_eth_clk:   std_logic;
72)     SIGNAL s_eth_rxd_d: std_logic_vector(3 DOWNTO 0);
73)     SIGNAL s_eth_rx_dv: std_logic;

74) 
75) BEGIN
76) 
77)     system: e_system
78)         PORT MAP (

79)             clk            => s_clk,
80)             pin_o_leds     => s_leds,
81)             pin_o_lcd      => s_lcd,
82)             pin_i_switches => (sw => (OTHERS => '0'), OTHERS => '0'),
83)             pin_i_uart_rx  => '1',
84)             pin_o_uart_tx  => s_uart,
85)             pin_i_eth      => s_i_eth,
86)             pin_o_eth      => s_o_eth

87)         );
88) 

89)     s_i_eth.rx_clk <= s_eth_clk;
90)     s_i_eth.rxd    <= "0" & s_eth_rxd_d;
91)     s_i_eth.rx_dv  <= s_eth_rx_dv;
92)     s_i_eth.crs    <= s_eth_rx_dv;
93)     s_i_eth.col    <= '0';
94)     s_i_eth.tx_clk <= s_eth_clk;

95) 
96)     p_clk: PROCESS

97)     BEGIN
98)         WHILE TRUE LOOP

99)             s_clk <= '0';

100)             WAIT FOR 10 ns;
101)             s_clk <= '1';
102)             WAIT FOR 10 ns;
103)         END LOOP;

104)     END PROCESS p_clk;
105) 
106)     p_eth_clk: PROCESS
107)     BEGIN
108)         WHILE TRUE LOOP
109)             s_eth_clk <= '0';
110)             WAIT FOR 20 ns;
111)             s_eth_clk <= '1';
112)             WAIT FOR 20 ns;
113)         END LOOP;
114)     END PROCESS p_eth_clk;
115) 

116)     p_eth_rx_data: PROCESS

117)     BEGIN

118)         s_eth_rxd_d <= "0000";

119)         s_eth_rx_dv <= '0';

120)         WAIT FOR 25 ms;

121)         WAIT UNTIL s_eth_clk = '1';
122)         WAIT UNTIL s_eth_clk = '0';
123)         FOR i IN 0 TO eth_data'length - 1 LOOP

124)             s_eth_rxd_d <= eth_data(i);

125)             s_eth_rx_dv <= '1';
126)             WAIT UNTIL s_eth_clk = '1';
127)             WAIT UNTIL s_eth_clk = '0';
128)         END LOOP;

129)         s_eth_rxd_d <= "0000";

130)         s_eth_rx_dv <= '0';
131)         WAIT;

132)     END PROCESS p_eth_rx_data;
133) 
134)     p_eth_tx_data: PROCESS
135)         VARIABLE l: line;
136)     BEGIN
137)         FOR i IN 0 TO eth_data'length - 1 LOOP
138)             WAIT UNTIL s_eth_clk = '0';
139)             WAIT UNTIL s_eth_clk = '1';

140)             IF s_o_eth.tx_en = '1' THEN

141)                 write(l, "ethernet TX: ");

142)                 write(l, to_integer(unsigned(s_o_eth.txd)));

143)                 writeline(output, l);
144)             END IF;
145)         END LOOP;
146)     END PROCESS p_eth_tx_data;