MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
records for ethernet pins
b8449ce @ 2012-04-08 12:45:21
| blocks | added file headers | 2012-04-08 11:54:40 |
|---|---|---|
| constraints | adapt ethernet TX clock timing constraint to transmission of data on falling edge | 2012-03-07 21:18:54 |
| doc | MIPS ISA spec | 2012-01-24 21:41:27 |
| fw | added file headers | 2012-04-08 11:54:40 |
| io | records for ethernet pins | 2012-04-08 12:45:21 |
| memory_maps | added file headers | 2012-04-08 11:54:40 |
| mips | added file headers | 2012-04-08 11:54:40 |
| stuff | added file headers | 2012-04-08 11:54:40 |
| system | records for ethernet pins | 2012-04-08 12:45:21 |
| test | records for ethernet pins | 2012-04-08 12:45:21 |
| .gitignore | Xilinx 13.4 | 2012-03-24 23:14:15 |
| Default.wcfg | project file update, DHCP seems to work now | 2012-04-05 21:59:57 |
| mips_sys.ipf | project file update | 2012-04-03 20:25:16 |
| mips_sys.xise | records for ethernet pins | 2012-04-08 12:45:21 |