MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
implemented ethernet RX CRC check
e4ce80e @ 2012-03-03 17:09:36
| .. | ||
|---|---|---|
| eth.vhd | implemented ethernet RX frame detection | 2012-03-03 16:13:53 |
| rst.vhd | begin of ethernet RX implementation, so far only test interface to core, does not meet timing | 2012-02-20 21:16:03 |
| rxframe.vhd | implemented ethernet RX CRC check | 2012-03-03 17:09:36 |
| rxif.vhd | begin of ethernet RX implementation, so far only test interface to core, does not meet timing | 2012-02-20 21:16:03 |