MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
adapt ethernet TX clock timing constraint to transmission of data on falling edge
de380fe @ 2012-03-07 21:18:54
| .. | ||
|---|---|---|
| crc32.vhd | implemented ethernet RX CRC check | 2012-03-03 17:09:36 |
| fifo.vhd | fixed FIFO implementation | 2012-03-06 20:47:36 |
| rwram.vhd | added FIFO to UART TX | 2012-02-20 13:00:00 |