MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
progmem 8KB -> 16KB
d1693e8 @ 2012-03-24 19:04:32
| .. | ||
|---|---|---|
| eth.vhd | handle eth TX packets of odd size in HW | 2012-03-24 17:30:33 |
| rst.vhd | begin of ethernet RX implementation, so far only test interface to core, does not meet timing | 2012-02-20 21:16:03 |
| rxframe.vhd | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |
| rxif.vhd | replaced ethernet RX clock domain crossing interface with dual clock FIFO | 2012-03-10 17:43:57 |
| txframe.vhd | handle padding to minimum ethernet frame size (TX) in HW | 2012-03-24 16:42:53 |
| txif.vhd | remove unneeded type definition | 2012-03-10 11:16:40 |