MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
.. | ||
---|---|---|
alu.vhd | added decoding of simple load/store instructions and lui instruction implemented lui instruction fix syntax bug in regs | 2012-01-26 20:50:15 |
cmp.vhd | if not comparing, jump is unconditional, so compare must return true | 2012-02-10 22:45:59 |
core.vhd | fixed instruction fetch during stall | 2012-02-09 21:31:07 |
decoder.vhd | fixed decoding jump instructions | 2012-02-10 22:45:29 |
div.vhd | implemented divider | 2012-02-05 20:59:58 |
mul_fast.vhd | second version of multiplier (slower, i.e. more stages -> faster clock) | 2012-02-05 21:39:45 |
mul_slow.vhd | second version of multiplier (slower, i.e. more stages -> faster clock) | 2012-02-05 21:39:45 |
regs.vhd | fix sensitivity lists | 2012-02-05 13:21:46 |
shifter.vhd | fix unused signals | 2012-02-05 13:21:27 |
types.vhd | decoding MULT(U)/DIV(U) -> MIPSel1 decoder complete | 2012-02-05 17:32:53 |