MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Stefan Schuermans Stefan Schuermans second version of multiplier (slower, i.e. more stages -> faster clock) 9225422 @ 2012-02-05 21:39:45
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clk.ucf start of MIPS core: begin of decoder and ALU 2012-01-23 22:06:18
rst.ucf start of MIPS core: begin of decoder and ALU 2012-01-23 22:06:18