MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy
65b2622 @ 2012-02-21 20:40:30
| .. | ||
|---|---|---|
| eth | begin of ethernet RX implementation, so far only test interface to core, does not meet timing | 2012-02-20 21:16:03 |
| cyc_cnt.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| lcd.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| lcd_pins.vhd | implemented LCD peripheral | 2012-02-12 15:31:45 |
| leds.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| switches.vhd | implemented displaying rotary counter (octal) | 2012-02-12 21:51:32 |
| switches_pins.vhd | implemented switches | 2012-02-12 20:47:12 |
| uart.vhd | added FIFO to UART RX | 2012-02-20 13:36:12 |