MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Stefan Schuermans Stefan Schuermans begin of ethernet RX implementation, so far only test interface to core, does not meet timing 47f05ce @ 2012-02-20 21:16:03
..
clk.ucf start of MIPS core: begin of decoder and ALU 2012-01-23 22:06:18
eth.ucf begin of ethernet RX implementation, so far only test interface to core, does not meet timing 2012-02-20 21:16:03
lcd.ucf implemented LCD peripheral 2012-02-12 15:31:45
leds.ucf LED output pins 2012-02-10 23:05:59
switches.ucf implemented switches 2012-02-12 20:47:12
uart.ucf fix UART TX pin 2012-02-20 14:16:22