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47f05ce
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master
mips_sys
constraints
eth.ucf
begin of ethernet RX implementation, so far only test interface to core, does not meet timing
Stefan Schuermans
commited
47f05ce
at 2012-02-20 21:16:03
eth.ucf
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NET "pin_o_eth_nrst" LOC = "D15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4; NET "pin_i_eth_rx_clk" LOC = "C12" | IOSTANDARD = LVCMOS33; NET "pin_i_eth_rxd[0]" LOC = "G7" | IOSTANDARD = LVCMOS33 | PULLUP; NET "pin_i_eth_rxd[1]" LOC = "G8" | IOSTANDARD = LVCMOS33 | PULLUP; NET "pin_i_eth_rxd[2]" LOC = "G9" | IOSTANDARD = LVCMOS33 | PULLUP; NET "pin_i_eth_rxd[3]" LOC = "H9" | IOSTANDARD = LVCMOS33 | PULLUP; NET "pin_i_eth_rxd[4]" LOC = "G10" | IOSTANDARD = LVCMOS33; NET "pin_i_eth_rx_dv" LOC = "H10" | IOSTANDARD = LVCMOS33 ; NET "pin_i_eth_crs" LOC = "H12" | IOSTANDARD = LVCMOS33; NET "pin_i_eth_col" LOC = "G12" | IOSTANDARD = LVCMOS33 | PULLDOWN; NET "pin_i_eth_tx_clk" LOC = "E11" | IOSTANDARD = LVCMOS33; NET "pin_o_eth_txd[0]" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 4; NET "pin_o_eth_txd[1]" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 4; NET "pin_o_eth_txd[2]" LOC = "E6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 4; NET "pin_o_eth_txd[3]" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 4; NET "pin_o_eth_tx_en" LOC = "D8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 4;
