MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
handle padding to minimum ethernet frame size (TX) in HW
2a4b80d @ 2012-03-24 16:42:53
| .. | ||
|---|---|---|
| eth | handle padding to minimum ethernet frame size (TX) in HW | 2012-03-24 16:42:53 |
| cyc_cnt.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| lcd.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| lcd_pins.vhd | implemented LCD peripheral | 2012-02-12 15:31:45 |
| leds.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| switches.vhd | implemented displaying rotary counter (octal) | 2012-02-12 21:51:32 |
| switches_pins.vhd | implemented switches | 2012-02-12 20:47:12 |
| uart.vhd | add read_enable signal to data bus and some peripherals | 2012-02-26 21:20:53 |