mips_sys

MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Tree: 230fe3b7e797cce9a8a42e7b8cca5d49eb381994
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Stefan Schuermans Stefan Schuermans fixed FIFO implementation 230fe3b @ 2012-03-06 20:47:36
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.gitignore implemented loading of data memory from firmware 2012-02-12 17:47:50
Makefile begin of ethernet RX implementation, so far only test interface to core, does not meet timing 2012-02-20 21:16:03
boot.s increased code and data address range to 8KB 2012-02-20 15:55:19
cyc_cnt.c converted code to use constants in data memory 2012-02-12 18:24:53
cyc_cnt.h implemented LCD peripheral 2012-02-12 15:31:45
eth.c implemented ethernet TX firmware 2012-03-06 18:59:32
eth.h implemented ethernet TX firmware 2012-03-06 18:59:32
lcd.c output character/string to LCD 2012-02-12 20:46:27
lcd.h output character/string to LCD 2012-02-12 20:46:27
leds.c converted code to use constants in data memory 2012-02-12 18:24:53
leds.h added "LEDs" I/O peripheral changed instruction memory from dpram to generated rom improved firmware structure to generate rom VHDL code 2012-02-10 22:43:28
lnk.cmd implemented ethernet RX busmaster -> packet reception working 2012-03-03 23:42:55
main.c implemented ethernet TX firmware 2012-03-06 18:59:32
ram.pl implemented loading of data memory from firmware 2012-02-12 17:47:50
rom.pl implemented loading of data memory from firmware 2012-02-12 17:47:50
switches.c implemented displaying rotary counter (octal) 2012-02-12 21:51:32
switches.h implemented displaying rotary counter (octal) 2012-02-12 21:51:32
uart.c add read_enable signal to data bus and some peripherals 2012-02-26 21:20:53
uart.h add UART error check to FW 2012-02-20 16:03:28