mips_sys

MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Tree: 12f75e02a37862df28cbbbffa9f8abd82819e9f2
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Stefan Schuermans Stefan Schuermans implemented multi-master feature for data bus extended ethernet block to have busmaster signals (dummy functionality up to now) 12f75e0 @ 2012-03-01 21:24:14
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eth.vhd implemented multi-master feature for data bus extended ethernet block to have busmaster signals (dummy functionality up to now) 2012-03-01 21:24:14
rst.vhd begin of ethernet RX implementation, so far only test interface to core, does not meet timing 2012-02-20 21:16:03
rxif.vhd begin of ethernet RX implementation, so far only test interface to core, does not meet timing 2012-02-20 21:16:03