https://git.blinkenarea.org/mips_sys/tree/12f75e02a37862df28cbbbffa9f8abd82819e9f2Recent commits to mips_sys (12f75e02a37862df28cbbbffa9f8abd82819e9f2)2012-03-01T21:24:14+00:00tag:gitlist.org,2012:commit/12f75e02a37862df28cbbbffa9f8abd82819e9f2implemented multi-master feature for data bus extended ethernet block to have busmaster signals (dummy functionality up to now)2012-03-01T21:24:14+00:00Stefan Schuermansstefan@schuermans.info
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tag:gitlist.org,2012:commit/77114e63cc8fb1d2d64a437ee5bebc61b7121753converted core to use req and grant signals to access data bus2012-03-01T21:23:47+00:00Stefan Schuermansstefan@schuermans.info
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tag:gitlist.org,2012:commit/1d0a24ccc53079418a318393e40398d23ac421fdkeep read enable active during read2012-03-01T20:04:09+00:00Stefan Schuermansstefan@schuermans.info
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tag:gitlist.org,2012:commit/4059dff66b96d3920d70dcf569785f45ef4e8367changed MIPS core to use read and write ack instead of stall input2012-02-29T21:28:37+00:00Stefan Schuermansstefan@schuermans.info
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tag:gitlist.org,2012:commit/c559f2fe8b700ba22f5ae8a98e5d7bba818f209ashortcut to switch between HW and simulation config2012-02-29T21:28:34+00:00Stefan Schuermansstefan@schuermans.info
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tag:gitlist.org,2012:commit/22b456946e289c89da296dcaceeb18de71761713add read_enable signal to data bus and some peripherals2012-02-26T21:20:53+00:00Stefan Schuermansstefan@schuermans.info
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tag:gitlist.org,2012:commit/318917987ee9e1b173da8adcb10b30513c38f925fix reading (1 cycle latency) from ethernet peripheral2012-02-26T18:26:02+00:00Stefan Schuermansstefan@schuermans.info
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tag:gitlist.org,2012:commit/e8985095f2186f2da5f9efaf5b16ee465ecbf7ectiming for ethernet clocks2012-02-21T21:39:56+00:00Stefan Schuermansstefan@schuermans.info
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tag:gitlist.org,2012:commit/65b262222298e6553b9748bee885da8c15da7365removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy2012-02-21T20:40:30+00:00Stefan Schuermansstefan@schuermans.info
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tag:gitlist.org,2012:commit/47f05ce618f31c873c88ab640434eacbf4513740begin of ethernet RX implementation, so far only test interface to core, does not meet timing2012-02-20T21:16:03+00:00Stefan Schuermansstefan@schuermans.info
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