test/testbed.vhd (6f152d9) - mips_sys · BlinkenArea

testbed.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE std.textio.all;
USE work.io_lcd_pins.all;
USE work.io_switches_pins.all;

ENTITY e_testbed IS
END ENTITY e_testbed;

ARCHITECTURE a_testbed OF e_testbed IS

COMPONENT e_system IS
        PORT (
            clk:              IN  std_logic;
            pin_o_leds:       OUT std_logic_vector(7 DOWNTO 0);
            pin_o_lcd:        OUT t_io_lcd_pins;
            pin_i_switches:   IN  t_io_switches_pins;
            pin_i_uart_rx:    IN  std_logic;
            pin_o_uart_tx:    OUT std_logic;
            pin_i_eth_rx_clk: IN  std_logic;
            pin_i_eth_rxd:    IN  std_logic_vector(4 DOWNTO 0);
            pin_i_eth_rx_dv:  IN  std_logic;
            pin_i_eth_crs:    IN  std_logic;
            pin_i_eth_col:    IN  std_logic;
            pin_i_eth_tx_clk: IN  std_logic;
            pin_o_eth_txd:    OUT std_logic_vector(3 DOWNTO 0);
            pin_o_eth_tx_en:  OUT std_logic
        );
    END COMPONENT e_system;

TYPE t_eth_data IS ARRAY(0 TO 160 - 1) OF std_logic_vector(3 DOWNTO 0);
    CONSTANT eth_data: t_eth_data := (
        X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5",
        X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"D",
        X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"F",
        X"F", X"F", X"F", X"F", X"0", X"0", X"D", X"1",
        X"0", X"6", X"C", X"D", X"5", X"7", X"D", X"2",
        X"8", X"0", X"0", X"0", X"5", X"4", X"0", X"0",
        X"0", X"0", X"6", X"3", X"9", X"3", X"E", X"D",
        X"0", X"4", X"0", X"0", X"0", X"4", X"1", X"1",
        X"0", X"4", X"7", X"2", X"0", X"C", X"8", X"A",
        X"0", X"0", X"A", X"0", X"F", X"F", X"F", X"F",
        X"F", X"F", X"F", X"F", X"7", X"9", X"3", X"5",
        X"0", X"0", X"1", X"0", X"0", X"0", X"2", X"2",
        X"B", X"9", X"1", X"D", X"4", X"4", X"9", X"6",
        X"5", X"6", X"3", X"7", X"0", X"2", X"9", X"6",
        X"3", X"7", X"4", X"7", X"0", X"2", X"5", X"6",
        X"9", X"6", X"E", X"6", X"0", X"2", X"C", X"6",
        X"1", X"6", X"E", X"6", X"7", X"6", X"5", X"6",
        X"2", X"7", X"0", X"2", X"4", X"5", X"5", X"6",
        X"3", X"7", X"4", X"7", X"1", X"2", X"A", X"0",
        X"B", X"A", X"3", X"8", X"D", X"8", X"D", X"1"
        );

SIGNAL s_clk:             std_logic;
    SIGNAL s_eth_clk:         std_logic;
    SIGNAL s_eth_rxd:         std_logic_vector(3 DOWNTO 0);
    SIGNAL s_eth_rx_dv:       std_logic;
    SIGNAL pin_leds:          std_logic_vector(7 DOWNTO 0);
    SIGNAL pin_lcd:           t_io_lcd_pins;
    SIGNAL pin_uart_loopback: std_logic;
    SIGNAL pin_eth_rxd:       std_logic_vector(4 DOWNTO 0);
    SIGNAL pin_eth_txd:       std_logic_vector(3 DOWNTO 0);
    SIGNAL pin_eth_tx_en:     std_logic;

BEGIN

system: e_system
        PORT MAP (
            clk              => s_clk,
            pin_o_leds       => pin_leds,
            pin_o_lcd        => pin_lcd,
            pin_i_switches   => (sw => (OTHERS => '0'), OTHERS => '0'),
            pin_i_uart_rx    => pin_uart_loopback,
            pin_o_uart_tx    => pin_uart_loopback,
            pin_i_eth_rx_clk => s_eth_clk,
            pin_i_eth_rxd    => pin_eth_rxd,
            pin_i_eth_rx_dv  => s_eth_rx_dv,
            pin_i_eth_crs    => s_eth_rx_dv,
            pin_i_eth_col    => '0',
            pin_i_eth_tx_clk => s_eth_clk,
            pin_o_eth_txd    => pin_eth_txd,
            pin_o_eth_tx_en  => pin_eth_tx_en
        );

pin_eth_rxd <= "0" & s_eth_rxd;

p_clk: PROCESS
    BEGIN
        WHILE TRUE LOOP
            s_clk <= '0';
            WAIT FOR 10 ns;
            s_clk <= '1';
            WAIT FOR 10 ns;
        END LOOP;
    END PROCESS p_clk;

p_eth_clk: PROCESS
    BEGIN
        WHILE TRUE LOOP
            s_eth_clk <= '0';
            WAIT FOR 20 ns;
            s_eth_clk <= '1';
            WAIT FOR 20 ns;
        END LOOP;
    END PROCESS p_eth_clk;

p_eth_data: PROCESS
    BEGIN
        s_eth_rxd   <= "0000";
        s_eth_rx_dv <= '0';
        WAIT FOR 1 ms;
        WAIT UNTIL s_eth_clk = '1';
        WAIT UNTIL s_eth_clk = '0';
        FOR i IN 0 TO eth_data'length - 1 LOOP
            s_eth_rxd   <= eth_data(i);
            s_eth_rx_dv <= '1';
            WAIT UNTIL s_eth_clk = '1';
            WAIT UNTIL s_eth_clk = '0';
        END LOOP;
        s_eth_rxd   <= "0000";
        s_eth_rx_dv <= '0';
        WAIT;
    END PROCESS p_eth_data;

END ARCHITECTURE a_testbed;

mips_sys

implemented ethernet RX packet and TX clock in testbed