mips_sys

1) LIBRARY IEEE;
2) USE IEEE.STD_LOGIC_1164.ALL;
3) USE IEEE.NUMERIC_STD.ALL;
4) 
5) ENTITY e_io_cyc_cnt IS
6)     PORT (

7)         rst:       IN  std_logic;
8)         clk:       IN  std_logic;
9)         o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
10)         i_wr_data: IN  std_logic_vector(31 DOWNTO 0);
11)         i_wr_en:   IN  std_logic

12)     );
13) END ENTITY e_io_cyc_cnt;
14) 
15) ARCHITECTURE a_io_cyc_cnt OF e_io_cyc_cnt IS
16) 
17)     SIGNAL n_cnt: std_logic_vector(31 DOWNTO 0);

18)     SIGNAL r_cnt: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');