mips_sys

Tree: 9225422
9225422606307faebd95da10e64f79b8604663f4
Stefan Schuermans moved multiplier to own module

Stefan Schuermans authored 12 years ago

 
mips/mul.vhd        1) LIBRARY ieee;
mips/mul.vhd        2) USE ieee.std_logic_1164.all;
mips/mul.vhd        3) USE ieee.numeric_std.all;
mips/mul.vhd        4) USE work.mips_types.all;
mips/mul.vhd        5) 
mips/mul.vhd        6) ENTITY e_mips_mul IS
mips/mul.vhd        7)     PORT (
mips/mul.vhd        8)         rst:      IN  std_logic;
mips/mul.vhd        9)         clk:      IN  std_logic;
mips/mul.vhd       10)         i_a:      IN  std_logic_vector(31 DOWNTO 0);
mips/mul.vhd       11)         i_b:      IN  std_logic_vector(31 DOWNTO 0);
mips/mul.vhd       12)         i_signed: IN  std_logic;
mips/mul.vhd       13)         i_start:  IN  std_logic;
mips/mul.vhd       14)         o_busy:   OUT std_logic;
mips/mul.vhd       15)         o_res:    OUT std_logic_vector(63 DOWNTO 0)
mips/mul.vhd       16)     );
mips/mul.vhd       17) END ENTITY e_mips_mul;
mips/mul.vhd       18) 
mips/mul.vhd       19) ARCHITECTURE a_mips_mul OF e_mips_mul IS
mips/mul.vhd       20)
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mips/mul_slow.vhd  21)     TYPE t_state IS (idle, mul1, add1, mul2, add2, mul3, add3, mul4, add4,
mips/mul_slow.vhd  22)                      post);
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mips/mul.vhd       23)     SIGNAL n_state: t_state;
mips/mul.vhd       24)     SIGNAL r_state: t_state;
mips/mul.vhd       25) 
mips/mul.vhd       26)     SIGNAL n_a:   unsigned(31 DOWNTO 0);
mips/mul.vhd       27)     SIGNAL n_b:   unsigned(31 DOWNTO 0);
mips/mul.vhd       28)     SIGNAL n_neg: boolean;
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mips/mul_slow.vhd  29)     SIGNAL n_r:   unsigned(31 DOWNTO 0);
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mips/mul.vhd       30)     SIGNAL n_res: unsigned(63 DOWNTO 0);
mips/mul.vhd       31)     SIGNAL r_a:   unsigned(31 DOWNTO 0);
mips/mul.vhd       32)     SIGNAL r_b:   unsigned(31 DOWNTO 0);
mips/mul.vhd       33)     SIGNAL r_neg: boolean;
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mips/mul_slow.vhd  34)     SIGNAL r_r:   unsigned(31 DOWNTO 0);
mips/mul_slow.vhd  35)     SIGNAL r_res: unsigned(63 DOWNTO 0);
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mips/mul.vhd       36) 
mips/mul.vhd       37) BEGIN
mips/mul.vhd       38)
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mips/mul_slow.vhd  39)     p_mul: PROCESS(r_state, r_a, r_b, r_neg, r_r, r_res,
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mips/mul.vhd       40)                    i_a, i_b, i_signed, i_start)
mips/mul.vhd       41)         VARIABLE v_a:   unsigned(15 DOWNTO 0);
mips/mul.vhd       42)         VARIABLE v_b:   unsigned(15 DOWNTO 0);
mips/mul.vhd       43)         VARIABLE v_res: unsigned(31 DOWNTO 0);
mips/mul.vhd       44)         VARIABLE v_add: unsigned(63 DOWNTO 0);
mips/mul.vhd       45)         VARIABLE v_sum: unsigned(63 DOWNTO 0);
mips/mul.vhd       46)     BEGIN
mips/mul.vhd       47)         o_busy  <= '0';
mips/mul.vhd       48)         n_state <= idle;
mips/mul.vhd       49)         n_a     <= r_a;
mips/mul.vhd       50)         n_b     <= r_b;
mips/mul.vhd       51)         n_neg   <= r_neg;
mips/mul.vhd       52)         n_res   <= r_res;
mips/mul.vhd       53)         v_a     := (OTHERS => '0');
mips/mul.vhd       54)         v_b     := (OTHERS => '0');
mips/mul.vhd       55)         v_add   := (OTHERS => '0');
mips/mul.vhd       56)         CASE r_state IS
mips/mul.vhd       57)             WHEN idle =>
mips/mul.vhd       58)                 IF i_start = '1' THEN
mips/mul.vhd       59)                     o_busy  <= '1';
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mips/mul_slow.vhd  60)                     n_state <= mul1;
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mips/mul.vhd       61)                     IF i_signed = '1' THEN
mips/mul.vhd       62)                         IF i_a(31) = '1' THEN
mips/mul.vhd       63)                             n_a <= unsigned(-signed(i_a));
mips/mul.vhd       64)                         ELSE
mips/mul.vhd       65)                             n_a <= unsigned(i_a);
mips/mul.vhd       66)                         END IF;
mips/mul.vhd       67)                         IF i_b(31) = '1' THEN
mips/mul.vhd       68)                             n_b <= unsigned(-signed(i_b));
mips/mul.vhd       69)                         ELSE
mips/mul.vhd       70)                             n_b <= unsigned(i_b);
mips/mul.vhd       71)                         END IF;
mips/mul.vhd       72)                         n_neg <= i_a(31) = '1' XOR i_b(31) = '1';
mips/mul.vhd       73)                     ELSE
mips/mul.vhd       74)                         n_a   <= unsigned(i_a);
mips/mul.vhd       75)                         n_b   <= unsigned(i_b);
mips/mul.vhd       76)                         n_neg <= false;
mips/mul.vhd       77)                     END IF;
mips/mul.vhd       78)                 END IF;
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mips/mul_slow.vhd  79)             WHEN mul1 =>
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mips/mul.vhd       80)                 o_busy  <= '1';
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mips/mul_slow.vhd  81)                 n_state <= add1;
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mips/mul.vhd       82)                 v_a     := r_a(15 DOWNTO  0);
mips/mul.vhd       83)                 v_b     := r_b(15 DOWNTO  0);
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mips/mul_slow.vhd  84)             WHEN add1 =>
mips/mul_slow.vhd  85)                 o_busy  <= '1';
mips/mul_slow.vhd  86)                 n_state <= mul2;
mips/mul_slow.vhd  87)                 v_add := X"00000000" & r_r;
mips/mul_slow.vhd  88)             WHEN mul2 =>
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mips/mul.vhd       89)                 o_busy  <= '1';
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mips/mul_slow.vhd  90)                 n_state <= add2;
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mips/mul.vhd       91)                 v_a     := r_a(31 DOWNTO 16);
mips/mul.vhd       92)                 v_b     := r_b(15 DOWNTO  0);
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mips/mul_slow.vhd  93)             WHEN add2 =>
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mips/mul.vhd       94)                 o_busy  <= '1';
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mips/mul_slow.vhd  95)                 n_state <= mul3;
mips/mul_slow.vhd  96)                 v_add := X"0000" & r_r & X"0000";
mips/mul_slow.vhd  97)             WHEN mul3 =>
mips/mul_slow.vhd  98)                 o_busy  <= '1';
mips/mul_slow.vhd  99)                 n_state <= add3;
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mips/mul.vhd      100)                 v_a     := r_a(15 DOWNTO  0);
mips/mul.vhd      101)                 v_b     := r_b(31 DOWNTO 16);
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mips/mul_slow.vhd 102)             WHEN add3 =>
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mips/mul.vhd      103)                 o_busy  <= '1';
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mips/mul_slow.vhd 104)                 n_state <= mul4;
mips/mul_slow.vhd 105)                 v_add := X"0000" & r_r & X"0000";
mips/mul_slow.vhd 106)             WHEN mul4 =>
mips/mul_slow.vhd 107)                 o_busy  <= '1';
mips/mul_slow.vhd 108)                 n_state <= add4;
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mips/mul.vhd      109)                 v_a     := r_a(31 DOWNTO 16);
mips/mul.vhd      110)                 v_b     := r_b(31 DOWNTO 16);
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mips/mul_slow.vhd 111)             WHEN add4 =>
mips/mul_slow.vhd 112)                 o_busy  <= '1';
mips/mul_slow.vhd 113)                 n_state <= post;
mips/mul_slow.vhd 114)                 v_add := r_r & X"00000000";
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mips/mul.vhd      115)             WHEN OTHERS => NULL;
mips/mul.vhd      116)         END CASE;
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mips/mul_slow.vhd 117)         n_r <= v_a * v_b;
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mips/mul.vhd      118)         v_sum := r_res + v_add;
mips/mul.vhd      119)         CASE r_state IS
mips/mul.vhd      120)             WHEN idle =>
mips/mul.vhd      121)                 n_res <= (OTHERS => '0');
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mips/mul_slow.vhd 122)             WHEN add1 | add2 | add3 | add4 =>
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mips/mul.vhd      123)                 n_res <= v_sum;
mips/mul.vhd      124)             WHEN post =>
mips/mul.vhd      125)                 IF r_neg THEN
mips/mul.vhd      126)                     n_res <= unsigned(-signed(r_res));
mips/mul.vhd      127)                 ELSE
mips/mul.vhd      128)                     n_res <= r_res;
mips/mul.vhd      129)                 END IF;
mips/mul.vhd      130)             WHEN OTHERS => NULL;
mips/mul.vhd      131)         END CASE;
mips/mul.vhd      132)     END PROCESS p_mul;
mips/mul.vhd      133) 
mips/mul.vhd      134)     p_sync: PROCESS(rst, clk)
mips/mul.vhd      135)     BEGIN
mips/mul.vhd      136)         IF rst = '1' THEN
mips/mul.vhd      137)             r_state <= idle;
mips/mul.vhd      138)             r_a     <= (OTHERS => '0');
mips/mul.vhd      139)             r_b     <= (OTHERS => '0');
mips/mul.vhd      140)             r_neg   <= false;
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mips/mul_slow.vhd 141)             r_r     <= (OTHERS => '0');
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mips/mul.vhd      142)             r_res   <= (OTHERS => '0');
mips/mul.vhd      143)         ELSIF rising_edge(clk) THEN
mips/mul.vhd      144)             r_state <= n_state;
mips/mul.vhd      145)             r_a     <= n_a;
mips/mul.vhd      146)             r_b     <= n_b;
mips/mul.vhd      147)             r_neg   <= n_neg;
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mips/mul_slow.vhd 148)             r_r     <= n_r;