mips_sys

1) LIBRARY IEEE;
2) USE IEEE.STD_LOGIC_1164.ALL;
3) USE IEEE.NUMERIC_STD.ALL;
4) 
5) ENTITY e_system IS
6)     PORT (

7)         rst:          IN  std_logic;
8)         clk:          IN  std_logic;
9)         i_core_stall: IN  std_logic;
10)         i_prg_addr:   IN  std_logic_vector(31 DOWNTO 0);
11)         i_prg_data:   IN  std_logic_vector(31 DOWNTO 0);
12)         i_prg_en:     IN  std_logic;
13)         o_dummy:      OUT std_logic_vector(31 DOWNTO 0)

14)     );
15) END ENTITY e_system;
16) 
17) ARCHITECTURE a_system OF e_system IS
18) 
19)     SIGNAL s_instr_addr:   std_logic_vector(31 DOWNTO 0);
20)     SIGNAL s_instr_data:   std_logic_vector(31 DOWNTO 0);
21)     SIGNAL s_data_addr:    std_logic_vector(31 DOWNTO 0);
22)     SIGNAL s_data_rd_data: std_logic_vector(31 DOWNTO 0);
23)     SIGNAL s_data_wr_data: std_logic_vector(31 DOWNTO 0);
24)     SIGNAL s_data_wr_en:   std_logic_vector( 3 DOWNTO 0);
25) 
26)     COMPONENT e_mips_core IS
27)         PORT (
28)             rst:            IN  std_logic;
29)             clk:            IN  std_logic;
30)             i_stall:        IN  std_logic;
31)             o_instr_addr:   OUT std_logic_vector(31 DOWNTO 0);
32)             i_instr_data:   IN  std_logic_vector(31 DOWNTO 0);
33)             o_data_addr:    OUT std_logic_vector(31 DOWNTO 0);
34)             i_data_rd_data: IN  std_logic_vector(31 DOWNTO 0);
35)             o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0);
36)             o_data_wr_en:   OUT std_logic_vector( 3 DOWNTO 0)
37)         );
38)     END COMPONENT e_mips_core;
39) 
40)     COMPONENT e_ram IS
41)         GENERIC (
42)             addr_width: natural;
43)             data_width: natural
44)         );
45)         PORT (
46)             clk:       IN  std_logic;
47)             i_addr:    IN  std_logic_vector(addr_width - 1 DOWNTO 0);
48)             o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
49)             i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
50)             i_wr_en:   IN  std_logic
51)         );
52)     END COMPONENT e_ram;
53) 
54)     COMPONENT e_dpram IS
55)         GENERIC (
56)             addr_width: natural;
57)             data_width: natural
58)         );
59)         PORT (
60)             clk:       IN  std_logic;
61)             i_rd_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
62)             o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
63)             i_wr_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
64)             i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
65)             i_wr_en:   IN  std_logic
66)         );
67)     END COMPONENT e_dpram;
68) 
69) BEGIN
70) 
71)     core: e_mips_core
72)         PORT MAP (
73)             rst            => rst,
74)             clk            => clk,

75)             i_stall        => i_core_stall,