MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
read peripherals with one cycle delay - as for memory
fe7741d @ 2012-02-12 19:10:11
| .. | ||
|---|---|---|
| clk.ucf | start of MIPS core: begin of decoder and ALU | 2012-01-23 22:06:18 |
| lcd.ucf | implemented LCD peripheral | 2012-02-12 15:31:45 |
| leds.ucf | LED output pins | 2012-02-10 23:05:59 |
| rst.ucf | start of MIPS core: begin of decoder and ALU | 2012-01-23 22:06:18 |