mips_sys

fixed uninitialized / not resetted frame done output of ethernet TX frame processing

Stefan Schuermans authored on 2012-03-10 10:56:08

added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing

Stefan Schuermans authored on 2012-03-10 10:50:55

send ethernet packet on center button press

Stefan Schuermans authored on 2012-03-07 21:52:08

ethernet TX function takes const pointer

Stefan Schuermans authored on 2012-03-07 21:19:40

adapt ethernet TX clock timing constraint to transmission of data on falling edge

Stefan Schuermans authored on 2012-03-07 21:18:54

fix CRC generation during ethernet transmission trigger CRC generator only once per byte get CRC value _after_ last byte

Stefan Schuermans authored on 2012-03-07 21:15:53

transmit data on falling edge of ethernet TX clock

Stefan Schuermans authored on 2012-03-07 21:15:19

implemented ethernet RX packet and TX clock in testbed

Stefan Schuermans authored on 2012-03-06 20:48:33

fixed FIFO implementation

Stefan Schuermans authored on 2012-03-06 20:47:36

more consistent DV and CRS handling

Stefan Schuermans authored on 2012-03-06 19:08:13