mips_sys

1) -- MIPS I system
2) -- Copyright 2011-2012 Stefan Schuermans <stefan@schuermans.info>
3) -- Copyleft GNU public license V2 or later
4) --          http://www.gnu.org/copyleft/gpl.html
5) 

6) LIBRARY ieee;
7) USE ieee.std_logic_1164.all;
8) USE ieee.numeric_std.all;
9) USE std.textio.all;

10) USE work.io_lcd_pins.all;

11) USE work.io_switches_pins.all;

12) 
13) ENTITY e_testbed IS
14) END ENTITY e_testbed;
15) 
16) ARCHITECTURE a_testbed OF e_testbed IS
17) 
18)     COMPONENT e_system IS
19)         PORT (

20)             clk:              IN  std_logic;
21)             pin_o_leds:       OUT std_logic_vector(7 DOWNTO 0);
22)             pin_o_lcd:        OUT t_io_lcd_pins;
23)             pin_i_switches:   IN  t_io_switches_pins;
24)             pin_i_uart_rx:    IN  std_logic;
25)             pin_o_uart_tx:    OUT std_logic;
26)             pin_i_eth_rx_clk: IN  std_logic;
27)             pin_i_eth_rxd:    IN  std_logic_vector(4 DOWNTO 0);
28)             pin_i_eth_rx_dv:  IN  std_logic;
29)             pin_i_eth_crs:    IN  std_logic;
30)             pin_i_eth_col:    IN  std_logic;
31)             pin_i_eth_tx_clk: IN  std_logic;
32)             pin_o_eth_txd:    OUT std_logic_vector(3 DOWNTO 0);
33)             pin_o_eth_tx_en:  OUT std_logic

34)         );
35)     END COMPONENT e_system;
36) 

37)     -- ICMP echo request
38)     TYPE t_eth_data IS ARRAY(0 TO 220 - 1) OF std_logic_vector(3 DOWNTO 0);

39)     CONSTANT eth_data: t_eth_data := (
40)         X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5",
41)         X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"D",

42)         X"2", X"0", X"D", X"4", X"9", X"4", X"0", X"5",
43)         X"3", X"5", X"1", X"0", X"0", X"0", X"D", X"1",
44)         X"0", X"6", X"C", X"D", X"5", X"7", X"D", X"2",
45)         X"8", X"0", X"0", X"0", X"5", X"4", X"0", X"0",
46)         X"0", X"0", X"4", X"5", X"0", X"0", X"0", X"0",
47)         X"0", X"4", X"0", X"0", X"0", X"4", X"1", X"0",
48)         X"8", X"B", X"5", X"F", X"0", X"C", X"8", X"A",
49)         X"0", X"0", X"A", X"0", X"0", X"C", X"8", X"A",
50)         X"0", X"0", X"9", X"5", X"8", X"0", X"0", X"0",
51)         X"E", X"8", X"7", X"5", X"F", X"0", X"2", X"6",
52)         X"0", X"0", X"1", X"0", X"6", X"E", X"4", X"B",
53)         X"D", X"6", X"F", X"4", X"0", X"0", X"0", X"0",
54)         X"0", X"0", X"0", X"0", X"4", X"4", X"E", X"6",
55)         X"3", X"0", X"0", X"0", X"0", X"0", X"0", X"0",
56)         X"0", X"0", X"0", X"0", X"0", X"1", X"1", X"1",
57)         X"2", X"1", X"3", X"1", X"4", X"1", X"5", X"1",
58)         X"6", X"1", X"7", X"1", X"8", X"1", X"9", X"1",
59)         X"A", X"1", X"B", X"1", X"C", X"1", X"D", X"1",
60)         X"E", X"1", X"F", X"1", X"0", X"2", X"1", X"2",
61)         X"2", X"2", X"3", X"2", X"4", X"2", X"5", X"2",
62)         X"6", X"2", X"7", X"2", X"8", X"2", X"9", X"2",
63)         X"A", X"2", X"B", X"2", X"C", X"2", X"D", X"2",
64)         X"E", X"2", X"F", X"2", X"0", X"3", X"1", X"3",
65)         X"2", X"3", X"3", X"3", X"4", X"3", X"5", X"3",
66)         X"6", X"3", X"7", X"3", X"2", X"9", X"1", X"C",
67)         X"0", X"1", X"2", X"C"

68)         );
69) 

70)     SIGNAL s_clk:       std_logic;
71)     SIGNAL s_leds:      std_logic_vector(7 DOWNTO 0);
72)     SIGNAL s_lcd:       t_io_lcd_pins;
73)     SIGNAL s_uart:      std_logic;
74)     SIGNAL s_eth_clk:   std_logic;
75)     SIGNAL s_eth_rxd_d: std_logic_vector(3 DOWNTO 0);
76)     SIGNAL s_eth_rxd:   std_logic_vector(4 DOWNTO 0);
77)     SIGNAL s_eth_rx_dv: std_logic;
78)     SIGNAL s_eth_txd:   std_logic_vector(3 DOWNTO 0);
79)     SIGNAL s_eth_tx_en: std_logic;

80) 
81) BEGIN
82) 
83)     system: e_system
84)         PORT MAP (

85)             clk              => s_clk,

86)             pin_o_leds       => s_leds,
87)             pin_o_lcd        => s_lcd,

88)             pin_i_switches   => (sw => (OTHERS => '0'), OTHERS => '0'),

89)             pin_i_uart_rx    => '1',
90)             pin_o_uart_tx    => s_uart,

91)             pin_i_eth_rx_clk => s_eth_clk,

92)             pin_i_eth_rxd    => s_eth_rxd,

93)             pin_i_eth_rx_dv  => s_eth_rx_dv,
94)             pin_i_eth_crs    => s_eth_rx_dv,

95)             pin_i_eth_col    => '0',

96)             pin_i_eth_tx_clk => s_eth_clk,

97)             pin_o_eth_txd    => s_eth_txd,
98)             pin_o_eth_tx_en  => s_eth_tx_en

99)         );
100) 

101)     s_eth_rxd <= "0" & s_eth_rxd_d;

102) 
103)     p_clk: PROCESS

104)     BEGIN
105)         WHILE TRUE LOOP

106)             s_clk <= '0';

107)             WAIT FOR 10 ns;
108)             s_clk <= '1';
109)             WAIT FOR 10 ns;
110)         END LOOP;

111)     END PROCESS p_clk;
112) 
113)     p_eth_clk: PROCESS
114)     BEGIN
115)         WHILE TRUE LOOP
116)             s_eth_clk <= '0';
117)             WAIT FOR 20 ns;
118)             s_eth_clk <= '1';
119)             WAIT FOR 20 ns;
120)         END LOOP;
121)     END PROCESS p_eth_clk;
122) 

123)     p_eth_rx_data: PROCESS

124)     BEGIN

125)         s_eth_rxd_d <= "0000";

126)         s_eth_rx_dv <= '0';

127)         WAIT FOR 25 ms;

128)         WAIT UNTIL s_eth_clk = '1';
129)         WAIT UNTIL s_eth_clk = '0';
130)         FOR i IN 0 TO eth_data'length - 1 LOOP

131)             s_eth_rxd_d <= eth_data(i);

132)             s_eth_rx_dv <= '1';
133)             WAIT UNTIL s_eth_clk = '1';
134)             WAIT UNTIL s_eth_clk = '0';
135)         END LOOP;

136)         s_eth_rxd_d <= "0000";

137)         s_eth_rx_dv <= '0';
138)         WAIT;

139)     END PROCESS p_eth_rx_data;
140) 
141)     p_eth_tx_data: PROCESS
142)         VARIABLE l: line;
143)     BEGIN
144)         FOR i IN 0 TO eth_data'length - 1 LOOP
145)             WAIT UNTIL s_eth_clk = '0';
146)             WAIT UNTIL s_eth_clk = '1';
147)             IF s_eth_tx_en = '1' THEN
148)                 write(l, "ethernet TX: ");
149)                 write(l, to_integer(unsigned(s_eth_txd)));
150)                 writeline(output, l);
151)             END IF;
152)         END LOOP;
153)     END PROCESS p_eth_tx_data;