mips_sys

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2) <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
3) 
4)   <header>
5)     <!-- ISE source project file created by Project Navigator.             -->
6)     <!--                                                                   -->
7)     <!-- This file contains project source information including a list of -->
8)     <!-- project source files, project and process properties.  This file, -->
9)     <!-- along with the project source files, is sufficient to open and    -->
10)     <!-- implement in ISE Project Navigator.                               -->
11)     <!--                                                                   -->
12)     <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
13)   </header>
14) 

15)   <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>

16) 
17)   <files>
18)     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">

19)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>

20)       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>

21)     </file>
22)     <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">

23)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>

24)       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>

25)     </file>
26)     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">

27)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>

28)       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>

29)     </file>
30)     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">

31)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>

32)       <association xil_pn:name="Implementation" xil_pn:seqID="22"/>

33)     </file>

34)     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">

35)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>

36)       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>

37)     </file>
38)     <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">

39)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>

40)       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>

41)     </file>

42)     <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">

43)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>

44)       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>

45)     </file>

46)     <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">

47)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>

48)       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>

49)     </file>

50)     <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">

51)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>

52)       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>

53)     </file>
54)     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">

55)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>

56)       <association xil_pn:name="Implementation" xil_pn:seqID="34"/>

57)     </file>

58)     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">

59)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>

60)       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
61)       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
62)       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>

63)     </file>

64)     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">

65)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>

66)       <association xil_pn:name="Implementation" xil_pn:seqID="29"/>

67)     </file>
68)     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">

69)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>

70)       <association xil_pn:name="Implementation" xil_pn:seqID="25"/>

71)     </file>
72)     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
73)       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>

74)     </file>

75)     <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">

76)       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>

77)     </file>

78)     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">

79)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>

80)       <association xil_pn:name="Implementation" xil_pn:seqID="28"/>

81)     </file>

82)     <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">

83)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>

84)       <association xil_pn:name="Implementation" xil_pn:seqID="26"/>

85)     </file>

86)     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">

87)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>

88)       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>

89)     </file>
90)     <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
91)       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>

92)     </file>

93)     <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">

94)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>

95)       <association xil_pn:name="Implementation" xil_pn:seqID="33"/>

96)     </file>
97)     <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">

98)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>

99)       <association xil_pn:name="Implementation" xil_pn:seqID="32"/>

100)     </file>

101)     <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">

102)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>

103)       <association xil_pn:name="Implementation" xil_pn:seqID="31"/>

104)     </file>

105)     <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">

106)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>

107)       <association xil_pn:name="Implementation" xil_pn:seqID="30"/>

108)     </file>

109)     <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">

110)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>

111)       <association xil_pn:name="Implementation" xil_pn:seqID="13"/>

112)     </file>

113)     <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">

114)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>

115)       <association xil_pn:name="Implementation" xil_pn:seqID="24"/>

116)     </file>
117)     <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
118)       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
119)     </file>
120)     <file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">

121)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>

122)       <association xil_pn:name="Implementation" xil_pn:seqID="23"/>

123)     </file>

124)     <file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">

125)       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>

126)     </file>

127)     <file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">

128)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>

129)       <association xil_pn:name="Implementation" xil_pn:seqID="21"/>

130)     </file>
131)     <file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">

132)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>

133)       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>

134)     </file>

135)     <file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">

136)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>

137)       <association xil_pn:name="Implementation" xil_pn:seqID="27"/>

138)     </file>
139)     <file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">

140)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>

141)       <association xil_pn:name="Implementation" xil_pn:seqID="19"/>

142)     </file>
143)     <file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">

144)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>

145)       <association xil_pn:name="Implementation" xil_pn:seqID="17"/>

146)     </file>
147)     <file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF">
148)       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
149)     </file>
150)     <file xil_pn:name="blocks/crc32.vhd" xil_pn:type="FILE_VHDL">

151)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>

152)       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>

153)     </file>

154)     <file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">

155)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>

156)       <association xil_pn:name="Implementation" xil_pn:seqID="18"/>

157)     </file>
158)     <file xil_pn:name="io/eth/txif.vhd" xil_pn:type="FILE_VHDL">

159)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>

160)       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>

161)     </file>
162)     <file xil_pn:name="io/eth/txframe.vhd" xil_pn:type="FILE_VHDL">

163)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>

164)       <association xil_pn:name="Implementation" xil_pn:seqID="16"/>

165)     </file>

166)     <file xil_pn:name="blocks/rwram_dc.vhd" xil_pn:type="FILE_VHDL">
167)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>

168)       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>

169)     </file>
170)     <file xil_pn:name="blocks/fifo_dc.vhd" xil_pn:type="FILE_VHDL">
171)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>

172)       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>

173)     </file>

174)     <file xil_pn:name="memory_maps/mips_sys.bmm" xil_pn:type="FILE_BMM">
175)       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
176)     </file>

177)     <file xil_pn:name="io/eth/pins.vhd" xil_pn:type="FILE_VHDL">
178)       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="226"/>
179)       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
180)     </file>

181)   </files>
182) 
183)   <properties>
184)     <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>

185)     <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/>

186)     <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
187)     <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
188)     <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
189)     <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
190)     <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
191)     <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
192)     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
193)     <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
194)     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>

195)     <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="true" xil_pn:valueState="non-default"/>

196)     <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
197)     <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
198)     <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
199)     <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
200)     <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
201)     <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
202)     <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
203)     <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
204)     <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
205)     <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
206)     <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
207)     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
208)     <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
209)     <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
210)     <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
211)     <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
212)     <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
213)     <property xil_pn:name="Configuration Rate" xil_pn:value="25" xil_pn:valueState="default"/>
214)     <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
215)     <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
216)     <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
217)     <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
218)     <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
219)     <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
220)     <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
221)     <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
222)     <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
223)     <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>

224)     <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="Default.wcfg" xil_pn:valueState="non-default"/>

225)     <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
226)     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
227)     <property xil_pn:name="Device" xil_pn:value="xc3s700a" xil_pn:valueState="non-default"/>
228)     <property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
229)     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
230)     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
231)     <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
232)     <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/>
233)     <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
234)     <property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/>
235)     <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
236)     <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
237)     <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
238)     <property xil_pn:name="Enable Filter on Suspend Input" xil_pn:value="Please use the ENABLE_SUSPEND implementation constraint." xil_pn:valueState="default"/>
239)     <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
240)     <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
241)     <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
242)     <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
243)     <property xil_pn:name="Enable Power-On Reset Detection" xil_pn:value="true" xil_pn:valueState="default"/>
244)     <property xil_pn:name="Enable Suspend/Wake Global Set/Reset" xil_pn:value="false" xil_pn:valueState="default"/>
245)     <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
246)     <property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3A Starter Kit" xil_pn:valueState="non-default"/>
247)     <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
248)     <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
249)     <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
250)     <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
251)     <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
252)     <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
253)     <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
254)     <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
255)     <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
256)     <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
257)     <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
258)     <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
259)     <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence" xil_pn:value="4" xil_pn:valueState="default"/>
260)     <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence" xil_pn:value="5" xil_pn:valueState="default"/>
261)     <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
262)     <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
263)     <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
264)     <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
265)     <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
266)     <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
267)     <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
268)     <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
269)     <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
270)     <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
271)     <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
272)     <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
273)     <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
274)     <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
275)     <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
276)     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
277)     <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
278)     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
279)     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
280)     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
281)     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
282)     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
283)     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
284)     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>

285)     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|e_system|a_system" xil_pn:valueState="non-default"/>
286)     <property xil_pn:name="Implementation Top File" xil_pn:value="system/system.vhd" xil_pn:valueState="non-default"/>
287)     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/e_system" xil_pn:valueState="non-default"/>

288)     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
289)     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
290)     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
291)     <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
292)     <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
293)     <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
294)     <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
295)     <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
296)     <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
297)     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
298)     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>

299)     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>

300)     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
301)     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
302)     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>

303)     <property xil_pn:name="Last Selected UCF File" xil_pn:value="/home/stefan/spartan3/mips_sys/constraints/clk.ucf" xil_pn:valueState="non-default"/>

304)     <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
305)     <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
306)     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
307)     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
308)     <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
309)     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
310)     <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
311)     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
312)     <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
313)     <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
314)     <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
315)     <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
316)     <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
317)     <property xil_pn:name="MultiBoot: Next Configuration Mode" xil_pn:value="001" xil_pn:valueState="default"/>
318)     <property xil_pn:name="MultiBoot: Starting Address for Next Configuration" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
319)     <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration" xil_pn:value="true" xil_pn:valueState="default"/>
320)     <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
321)     <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
322)     <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
323)     <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
324)     <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
325)     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
326)     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
327)     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>

328)     <property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>

329)     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>

330)     <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed" xil_pn:valueState="non-default"/>

331)     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
332)     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
333)     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
334)     <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
335)     <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
336)     <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
337)     <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
338)     <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
339)     <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
340)     <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
341)     <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
342)     <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
343)     <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
344)     <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
345)     <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
346)     <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
347)     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
348)     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
349)     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>

350)     <property xil_pn:name="Output File Name" xil_pn:value="e_system" xil_pn:valueState="default"/>

351)     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
352)     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
353)     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
354)     <property xil_pn:name="Package" xil_pn:value="fg484" xil_pn:valueState="non-default"/>
355)     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
356)     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>

357)     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>

358)     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="Standard" xil_pn:valueState="non-default"/>

359)     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
360)     <property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
361)     <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
362)     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>

363)     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="e_system_map.vhd" xil_pn:valueState="default"/>
364)     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="e_system_timesim.vhd" xil_pn:valueState="default"/>
365)     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="e_system_synthesis.vhd" xil_pn:valueState="default"/>
366)     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="e_system_translate.vhd" xil_pn:valueState="default"/>

367)     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
368)     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
369)     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
370)     <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
371)     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
372)     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
373)     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
374)     <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
375)     <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
376)     <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
377)     <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
378)     <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
379)     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
380)     <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
381)     <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
382)     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
383)     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
384)     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
385)     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>

386)     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="e_system" xil_pn:valueState="default"/>

387)     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
388)     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
389)     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
390)     <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
391)     <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
392)     <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
393)     <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
394)     <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
395)     <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
396)     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
397)     <property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/>
398)     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
399)     <property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/>
400)     <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
401)     <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
402)     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
403)     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
404)     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
405)     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
406)     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
407)     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>

408)     <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/e_testbed" xil_pn:valueState="non-default"/>
409)     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.e_testbed" xil_pn:valueState="non-default"/>

410)     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
411)     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
412)     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
413)     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
414)     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
415)     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
416)     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>

417)     <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1 ms" xil_pn:valueState="non-default"/>

418)     <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
419)     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
420)     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
421)     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
422)     <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
423)     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
424)     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>

425)     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.e_testbed" xil_pn:valueState="default"/>

426)     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
427)     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
428)     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
429)     <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
430)     <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
431)     <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
432)     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
433)     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
434)     <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
435)     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
436)     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
437)     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
438)     <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
439)     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
440)     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
441)     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
442)     <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
443)     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
444)     <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
445)     <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
446)     <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
447)     <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
448)     <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
449)     <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
450)     <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>

451)     <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>

452)     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
453)     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
454)     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
455)     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
456)     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
457)     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
458)     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
459)     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
460)     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>

461)     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>

462)     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
463)     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
464)     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
465)     <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
466)     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
467)     <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
468)     <property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
469)     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
470)     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
471)     <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>

472)     <property xil_pn:name="iMPACT Project File" xil_pn:value="mips_sys.ipf" xil_pn:valueState="non-default"/>

473)     <!--                                                                                  -->
474)     <!-- The following properties are for internal use only. These should not be modified.-->
475)     <!--                                                                                  -->

476)     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|e_testbed|a_testbed" xil_pn:valueState="non-default"/>

477)     <property xil_pn:name="PROP_DesignName" xil_pn:value="mips_sys" xil_pn:valueState="non-default"/>
478)     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
479)     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
480)     <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
481)     <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
482)     <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
483)     <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
484)     <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
485)     <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
486)     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-23T20:57:37" xil_pn:valueState="non-default"/>
487)     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="504447C81FC3113F3078F816935626AA" xil_pn:valueState="non-default"/>
488)     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
489)     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
490)   </properties>
491) 
492)   <bindings>

493)     <binding xil_pn:location="/e_system" xil_pn:name="constraints/leds.ucf"/>

494)     <binding xil_pn:location="/e_system" xil_pn:name="constraints/clk.ucf"/>

495)     <binding xil_pn:location="/e_system" xil_pn:name="constraints/lcd.ucf"/>

496)     <binding xil_pn:location="/e_system" xil_pn:name="constraints/switches.ucf"/>

497)     <binding xil_pn:location="/e_system" xil_pn:name="constraints/uart.ucf"/>

498)     <binding xil_pn:location="/e_system" xil_pn:name="constraints/eth.ucf"/>

499)     <binding xil_pn:location="/e_system" xil_pn:name="memory_maps/mips_sys.bmm"/>