MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
timing for ethernet clocks
e898509 @ 2012-02-21 21:39:56
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| system.vhd | removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy | 2012-02-21 20:40:30 |