MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
adapt ethernet TX clock timing constraint to transmission of data on falling edge
de380fe @ 2012-03-07 21:18:54
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| testbed.vhd | implemented ethernet RX packet and TX clock in testbed | 2012-03-06 20:48:33 |