MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
implement basic pseudo random number generator
af6f67d @ 2012-04-04 22:27:02
| .. | ||
|---|---|---|
| eth | improve ethernet busmaster (TX) critical path | 2012-04-03 20:23:25 |
| cyc_cnt.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| lcd.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| lcd_pins.vhd | implemented LCD peripheral | 2012-02-12 15:31:45 |
| leds.vhd | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| switches.vhd | debounce switches | 2012-04-03 20:23:39 |
| switches_pins.vhd | debounce switches | 2012-04-03 20:23:39 |
| uart.vhd | add read_enable signal to data bus and some peripherals | 2012-02-26 21:20:53 |