MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
implement basic pseudo random number generator
af6f67d @ 2012-04-04 22:27:02
| blocks | improve synchonous FIFO implementation (get rid of delays between reads) | 2012-03-11 18:59:11 |
|---|---|---|
| constraints | adapt ethernet TX clock timing constraint to transmission of data on falling edge | 2012-03-07 21:18:54 |
| doc | MIPS ISA spec | 2012-01-24 21:41:27 |
| fw | implement basic pseudo random number generator | 2012-04-04 22:27:02 |
| io | debounce switches | 2012-04-03 20:23:39 |
| memory_maps | remove generated file | 2012-04-03 20:24:29 |
| mips | fix divider (result) | 2012-03-21 22:11:20 |
| stuff | remove old exmaple packets | 2012-03-24 14:06:47 |
| system | progmem 8KB -> 16KB | 2012-03-24 19:04:32 |
| test | improve 200ms tick and task processing, get rid of UART output of received ethernet frames | 2012-03-24 19:05:42 |
| .gitignore | Xilinx 13.4 | 2012-03-24 23:14:15 |
| Default.wcfg | migration to Xilinx 13.4 | 2012-03-24 14:06:11 |
| mips_sys.ipf | project file update | 2012-04-03 20:25:16 |
| mips_sys.xise | infrastructure to change SW without re-synthesizing | 2012-03-25 02:16:26 |