MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Stefan Schuermans Stefan Schuermans fix ethernet TX firmware: pad packet with zeros to reach size divisible by 4 (TX cannot deal with other sizes) ab3c9fb @ 2012-03-19 23:32:26
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crc32.vhd implemented ethernet RX CRC check 2012-03-03 17:09:36
fifo.vhd improve synchonous FIFO implementation (get rid of delays between reads) 2012-03-11 18:59:11
fifo_dc.vhd remove leftover comments 2012-03-11 18:44:23
rwram.vhd added FIFO to UART TX 2012-02-20 13:00:00
rwram_dc.vhd added dual clock FIFO implementation changed ethernet TX interface to use dual clock FIFO for clock domain crossing 2012-03-10 10:50:55