MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
clock and reset constraints are for whole system
a086ce1 @ 2012-02-10 23:22:30
| .. | ||
|---|---|---|
| ram.vhd | implented basic system with core, instr memory, data memory | 2012-02-06 21:28:00 |
| system.vhd | whitespace fix | 2012-02-10 23:21:54 |