MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
clock and reset constraints are for whole system
a086ce1 @ 2012-02-10 23:22:30
| .. | ||
|---|---|---|
| clk.ucf | start of MIPS core: begin of decoder and ALU | 2012-01-23 22:06:18 |
| leds.ucf | LED output pins | 2012-02-10 23:05:59 |
| rst.ucf | start of MIPS core: begin of decoder and ALU | 2012-01-23 22:06:18 |