MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
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eth_pack.hex | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |
eth_pack.nib | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |
eth_tx_log_2_c_data.pl | script to convert testbed log to C data array | 2012-03-21 21:42:02 |