MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
fixed decoding of M[FT]{HI|LO}
48bb600 @ 2012-03-13 21:11:43
| .. | ||
|---|---|---|
| testbed.vhd | implemented ethernet RX packet and TX clock in testbed | 2012-03-06 20:48:33 |