MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
fix reading (1 cycle latency) from ethernet peripheral
3189179 @ 2012-02-26 18:26:02
| .. | ||
|---|---|---|
| system.vhd | removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy | 2012-02-21 20:40:30 |