MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system

Stefan Schuermans Stefan Schuermans handle padding to minimum ethernet frame size (TX) in HW 2a4b80d @ 2012-03-24 16:42:53
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system.vhd implemented ethernet TX frame generation and register interface (no firmware yet, no simulation testbed support yet, not tested yet) 2012-03-05 22:01:56